VARIABLE PRECISION FLOATING POINT MULTIPLY-ADD CIRCUIT
First Claim
1. An variable precision floating point circuit comprising:
- a variable precision mantissa unit to selectively operate in any one of a plurality of precision modes wherein in each precision mode a level of parallelism in the circuit is inversely proportional to a level of precision,multiple exponent units to selectively operate in one of a plurality of parallelism modes corresponding to a selected precision mode,and certainty calculation units to calculate certainty bounds of one or more outputs of the variable precision unit.
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Accused Products
Abstract
Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
76 Citations
27 Claims
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1. An variable precision floating point circuit comprising:
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a variable precision mantissa unit to selectively operate in any one of a plurality of precision modes wherein in each precision mode a level of parallelism in the circuit is inversely proportional to a level of precision, multiple exponent units to selectively operate in one of a plurality of parallelism modes corresponding to a selected precision mode, and certainty calculation units to calculate certainty bounds of one or more outputs of the variable precision unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system comprising:
a multiply-add circuit comprising; a variable precision mantissa unit to selectively operate in anyone of a plurality of precision modes, multiple exponent units to selectively operate in one of a plurality of parallelism corresponding to a selected precision mode, and certainty calculation units to calculate certainty bounds of output(s) of the variable precision unit. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A n-bit by n-bit multiplier circuit comprising:
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a parallelogram configured to set carries of a predetermined number (k) of least significant bits (LSBs) of a multiplication product to zero for a multiplication operation, and a detection circuit to induce a replay of the multiplication operation by the multiplier to generate a full multiplication result if necessary. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification