INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD

• US 20140189204A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamamoto, Akira, Homma, Shigeo, Sugimoto, Sadahiro
• Application Number:
  US13/812,285
• Publication Number:
  US 20140189204A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/21 Employing a record carrier using a specific recording technology
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/225 Hybrid cache memory, e.g. having both volatile and non-volatile portions
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

An information processing apparatus comprises a plurality types of cache memories having different characteristics, decides on a type of cache memory to be used as a data cache destination based on the access characteristics of cache-target data, and caches the data in the cache memory of the decided type.

Claims

1. An information processing apparatus configured to accept an I/O request from a host computer, comprising:

a plurality types of cache memories having different characteristics; and

a control device, which is coupled to the plurality types of cache memories,

wherein the control device;

caches, according to an access characteristic of data associated with the I/O request, the data in any one of the multiple type of the cache memories.

2. An information processing apparatus according to claim 1, wherein the plurality types of cache memories comprise a first cache memory composed of first memory, and a second cache memory composed of second memory having lower access performance than the first cache memory.

3. An information processing apparatus according to claim 2, wherein the control device caches data having higher access frequency than a pre-determined threshold preferentially in the first cache memory over the second cache memory.

4. An information processing apparatus according to claim 3, wherein the control device preferentially caches the data in the second cache memory over the first cache memory in a case where the access rate for the data is slower than the threshold.

5. An information processing apparatus according to claim 4, wherein the control device:

collects, for each prescribed region in one or more logical volumes in which data is managed, information related to access with respect to data of the region; and

decides on the threshold related to the access rate based on the information related to access.

6. An information processing apparatus according to claim 3, further comprising:

a buffer memory having higher access performance than the second cache memory,

wherein when storing the data in the second cache memory, the control device stores the data in the buffer memory, and thereafter, stores the data in the second cache memory from the buffer memory.

7. An information processing apparatus according to claim 3, wherein the first memory is a RAM (Random Access Memory), and the second memory is a flash memory.

8. An information processing apparatus according to claim 3, wherein the control device cashes the data preferentially in the first cache memory over the second cache memory in a case where the data is target data of a sequential access.

9. An information processing apparatus according to claim 3, wherein the control device caches the data preferentially in the first cache memory in a case where a storage device in which the data is ultimately managed is comprised of the second memory.

10. An information processing apparatus according to claim 3, wherein the control device cashes the data preferentially in the first cache memory in a case where the data is used temporarily.

11. An information processing apparatus according to claim 1, wherein the plurality types of cache memories are a third cache memory comprised of a third memory, and a fourth cache memory for which the number of data updates is restricted more than the third memory, and the control device cashes data having a high update frequency preferentially in the third cache memory over the fourth cache memory.

12. An information processing apparatus according to claim 11, wherein the third memory is a RAM, and the fourth memory is a flash memory.

13. An information processing apparatus configured to accept an I/O request from a host computer, comprising:

a first cache memory which is composed of a RAM and has multiple segments;

a second cache memory which is composed of a nonvolatile memory and has multiple segments;

a control device, which is coupled to the first cache memory and the second cache memory, manages a cache directory comprising multiple entries;

wherein;

each entry has a correspondence relationship between a logical address of cached data and information related to a storage location in which the data is cached;

the information related to the storage location is information specifying a segment in the first cache memory in which the data is stored in a case where the data is cached in the first cache memory; and

the information related to the storage location is information specifying a segment in the second cache memory in which the data is stored in a case where the data is cached in the second cache memory.

14. An information processing apparatus according to claim 13, wherein the control device allocates a segment of either the first or the second cache memory for caching the data, and registers an entry, which stores correspondence relationship between the logical address and information specifying the allocated segment, in the cache directory, in a case where a logical address of data associated with the I/O request does not exist in the multiple entries which the cache directory has.

15. An information processing apparatus according to claim 13, wherein the control device caches data having higher access frequency than a predetermined threshold preferentially in the first cache memory over the second cache memory.

16. An information processing apparatus according to claim 13, wherein the control device cashes the data preferentially in the first cache memory over the second cache memory in a case where the data is target data of a sequential access.

17. A cache control method, comprising:

accepting, an I/O request from a host computer; and

caching, according to an access characteristic of data associated with the I/O request, the data in any one of multiple cache memories having different characteristics.

18. A cache control method according to claim 17, wherein the multiple cache memories comprise a first cache memory comprised of a RAM, and a second cache memory comprised of a flash memory, and caching the data having higher access frequency than a pre-determined threshold preferentially in the first cache memory over the second cache memory.

19. A cache control method according to claim 17, wherein the multiple of cache memories comprise a first cache memory comprised of a RAM, and a second cache memory comprised of a flash memory, and caching the data preferentially in the first cache memory over the second cache memory in a case where the data is target data of a sequential access.