METHOD AND SYSTEM FOR MANAGING PROGRAM CYCLES IN A MULTI-LAYER MEMORY

• US 20140189205A1
• Filed: 03/14/2013
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sinclair, Alan Welsh, Thomas, Nicholas James, Wright, Barry
• Granted Patent: US 9,336,133 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A system and method for managing program cycles in a multi-layer memory is disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request and an amount of data already programmed in the plurality of memory layers necessary to be programmed in maintenance operations to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the request, and the amount of data already programmed to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle.

Claims

1. A method of managing data comprising:

in a memory system having an interface for receiving data from a host, at least one flash memory die having a plurality of layers, each of the plurality of layers having a different bit-per-cell data capacity, and a controller in communication with the interface and the at least one flash memory die, the controller;

receiving requests to program data from a host;

determining a program cycle, in advance of programming data associated with the requests, the programming cycle comprising a set of a host data write programming operation and maintenance programming operations in at least one of the plurality of layers, for programming an amount of host data associated with the received requests and freeing an amount of memory capacity for a subsequent host data write programming operation; and

after determining the programming cycle, executing the host data write programming operation and any maintenance program operations in the determined programming cycle.

2. The method of claim 1, wherein determining programming cycle comprises determining the programming cycle for a predetermined amount of host data.

3. The method of claim 2, wherein the predetermined amount comprises a programming unit having a fixed number of metapages that is a lowest common multiple of a whole number of metablocks in each of the plurality of layers.

4. The method of claim 2, further comprising determining an amount of data necessary to be programmed in the maintenance programming operations by reviewing a status of each of the plurality of layers of the flash memory die and determining a number of maintenance operations required to free an amount of space sufficient to program the predetermined amount of host data in response to a subsequent request to program data without a need for prior maintenance operations.

5. The method of claim 4, wherein reviewing the status of each of the plurality of layers comprises determining at least one of a presence of a minimum number of free blocks in each layer or an amount of valid data programmed in each of the plurality of layers.

6. The method of claim 4, wherein determining the program cycle comprises selecting one of a predetermined plurality of program cycle types based on a status of a destination layer for the predetermined amount of host data and a status of each higher bit-per-cell layer identified in the program cycle types.

7. The method of claim 6, wherein the at least one flash memory die comprises a plurality of flash memory die and wherein determining the program cycle comprises determining the program cycle for the destination layer in a first of the plurality of flash memory die and for at least one higher bit-per-cell layer linked to the destination layer in a different one of the plurality of flash memory die.

8. The method of claim 1, wherein each of the plurality of layers comprises a plurality of partitions, and each programmed block in a layer is exclusively classified as being in a respective one of the plurality of partitions in the layer;

and

wherein the method further comprises the controller;

determining if the data associated with the request to program data is associated with a particular one of the plurality of partitions; and

only permitting programming of the data associated with the request, and the amount of data already programmed to be programmed in maintenance operations, according to the determined program cycle when no other program cycle associated with the particular one of the plurality of partitions is active.

9. The method of claim 8, further comprising concurrently programming in one of the at least one flash memory die a first program cycle for data in a first host request associated with a first of the plurality of partitions and a second program cycle for data in a second host request associated with a second of the plurality of partitions.

10. A method of managing data comprising:

in a memory system having an interface for receiving data from a host, a plurality of flash memory die having a plurality of layers, each of the plurality of layers having a different bit-per-cell data capacity, and at least one controller in communication with the interface and the plurality of flash memory die, the controller;

receiving requests to program data from a host;

selecting one of the plurality of flash memory die in which to execute a program cycle;

prior to programming data associated with the request, selecting a program cycle type from a predetermined number of program cycle types based on a type of data associated with the request and a status of each of the plurality of layers in the selected flash memory die, wherein each of the predetermined number of program cycle types identifies a different combination of a host write programming operation and maintenance programming operations for completing a program cycle, and wherein the program cycle comprises writing a predetermined amount of data received from the host and executing an amount of maintenance programming operations such that sufficient memory capacity in each layer to which data is programmed during the selected program cycle is freed to program an additional amount of data in a next program cycle without triggering a prior maintenance operation; and

executing the host data write programming operation and any maintenance program operations according to the selected program cycle type.

11. The method of claim 10, wherein each of the plurality of layers in the flash memory die comprises a plurality of partitions associated with data of a respective type of data, and wherein selecting the programming cycle type comprises selecting one of the plurality of programming cycle types corresponding to a partition associated with the type of data in the request to program data.

12. The method of claim 10, wherein the predetermined amount of data comprises a programming unit having a fixed number of metapages that is a lowest common multiple of a whole number of metablocks in each of the plurality of layers.

13. The method of claim 12, wherein selecting the program cycle type comprises selecting the program cycle type based on at least one of a presence of a minimum number of free blocks in each layer or an amount of valid data programmed in each layer of the selected flash memory die.

14. A mass storage memory system, comprising:

an interface adapted to receive data from a host system;

at least one flash memory die having a plurality of layers, each of the plurality of layers having a different bit-per-cell data capacity and a plurality of memory blocks; and

a controller in communication with the interface and the flash memory die, the controller configured to;

receive requests to program data from the host system;

in advance of programming data associated with the request, determine a program cycle comprising a set of a host data write programming operation and maintenance programming operations in at least one of the plurality of layers, for programming an amount of host data associated with the received requests and freeing an amount of memory capacity for a subsequent host data write programming operation; and

after determining the programming cycle, execute the host data write programming operation and any maintenance program operations according to the determined programming cycle.

15. The mass storage memory system of claim 14, wherein the controller is configured to determine the programming cycle for a predetermined amount of host data.

16. The mass storage memory system of claim 15, wherein the predetermined amount of host data comprises a programming unit having a fixed number of metapages that is a lowest common multiple of a whole number of metablocks in each of the plurality of layers.

17. The mass storage memory system of claim 16, wherein to determine the maintenance operations on the amount of data already programmed, the controller is further configured to:

review a status of each of the plurality of layers of the memory die; and

determine a number of maintenance operations in each of the plurality of layers required to free an amount of space sufficient to program the predetermined amount of host data in response to a subsequent request to program data without a need for prior maintenance operations.

18. The mass storage memory system of claim 17, wherein the controller is configured to determine the status of each layer based on at least one of a presence of a minimum number of free blocks in each layer or an amount of valid data programmed for each layer.

19. The mass storage memory system of claim 17, wherein to determine the program cycle, the controller is configured to select one of a predetermined plurality of program cycle types based on a status of a destination layer for the data associated with the received request to program and a status of each higher bit-per-cell layer in which a maintenance operation is necessary.

20. The mass storage memory system of claim 19, wherein the at least one flash memory die comprises a plurality of flash memory die, and wherein the controller is configured to determine the program cycle for the destination layer in a first of the plurality of flash memory die and for at least one higher bit-per-cell layer linked to the destination layer in a different one of the plurality of flash memory die.