PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
First Claim
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1. A processor comprising:
- a plurality of logical processors each having one or more corresponding lower level caches;
a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and
logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor.
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Abstract
A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
55 Citations
23 Claims
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1. A processor comprising:
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a plurality of logical processors each having one or more corresponding lower level caches; a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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virtually clustering a plurality of logical processors into a virtual cluster, in which each of the logical processors has one or more corresponding lower level caches; and directing an access that misses in one or more lower level caches corresponding to a logical processor to a subset of distributed cache slices, of a shared higher level cache, that are in a virtual cluster that corresponds to the logical processor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A system comprising:
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an interconnect; a processor coupled with the interconnect, the processor including; a plurality of logical processors each having one or more corresponding lower level caches; and a shared higher level cache that is shared by the plurality of logical processors, in which the shared higher level cache includes a distributed cache slice for each of the logical processors; and a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing virtual cluster aware software, the virtual cluster aware software operable to preferentially allocate memory for a process running on a logical processor of a virtual cluster from memory corresponding to the virtual cluster. - View Dependent Claims (22, 23)
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Specification