MERGING EVICTION AND FILL BUFFERS FOR CACHE LINE TRANSACTIONS

• US 20140189245A1
• Filed: 12/31/2012
• Published: 07/03/2014
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Rupley, Jeff, Nakra, Tarun
• Granted Patent: US 9,244,841 B2
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

Claims

1. A processor, comprising:

a first cache memory; and

a bus unit comprising a plurality of buffers and operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in the first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

2. The processor of claim 1, further comprising a second cache memory, wherein the bus unit is operable to receive the first cache line from the second cache memory.

3. The processor of claim 2, wherein the bus unit is operable to transfer the eviction data from the selected buffer to the second cache memory and de-allocate the selected buffer.

4. The processor of claim 1, wherein the bus unit is operable to transfer the fill data to the first cache memory in parallel with storing the eviction data by transferring the fill data to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer.

5. The processor of claim 1, wherein the bus unit is operable to transfer the fill data from the selected buffer to the first cache memory and concurrently transfer the eviction data into the selected buffer.

6. The processor of claim 1, wherein the selected buffer is divided into a plurality of segments, the fill data is divided into a plurality of portions, one of the portions of the fill data is stored in each of the segments, the eviction data is divided into a plurality of portions, and the bus unit is further operable to transfer a first portion of the fill data stored in a first segment to the first cache memory, store a first portion of the eviction data in the first segment, and repeat the transferring of remaining portions of the fill data and the storing of portions of the eviction data for the remaining segments.

7. A system, comprising:

a system memory; and

a processor, the processor comprising;

a first cache memory; and

a bus unit comprising a plurality of buffers and operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in the first cache memory, receive the first cache line from the memory load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

8. The system of claim 7, wherein the bus unit is operable to receive the first cache line from the system memory.

9. The system of claim 7, further comprising a second cache memory, wherein the bus unit is operable to receive the first cache line from the second cache memory.

10. The system of claim 9, wherein the bus unit is operable to transfer the eviction data from the selected buffer to the second cache memory and de-allocate the selected buffer.

11. The system of claim 7, wherein the bus unit is operable to transfer the fill data to the first cache memory in parallel with storing the eviction data by transferring the fill data to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer.

12. The system of claim 7, wherein the bus unit is operable to transfer the fill data from the selected buffer to the first cache memory and concurrently transfer the eviction data into the selected buffer.

13. The system of claim 7, wherein the selected buffer is divided into a plurality of segments, the fill data is divided into a plurality of portions, one of the portions of the fill data is stored in each of the segments, the eviction data is divided into a plurality of portions, and the bus unit is further operable to transfer a first portion of the fill data stored in a first segment to the first cache memory, store a first portion of the eviction data in the first segment, and repeat the transferring of remaining portions of the fill data and the storing of portions of the eviction data for the remaining segments.

14. A method, comprising:

allocating a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory;

loading fill data from the first cache line into the selected buffer; and

transferring the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

15. The method of claim 14, further comprising receiving the first cache line from a system memory.

16. The method of claim 14, further comprising receiving the first cache line from a second cache memory.

17. The method of claim 16, further comprising:

transferring the eviction data from the selected buffer to the second cache memory; and

de-allocating the selected buffer.

18. The method of claim 14, wherein transferring the fill data to the first cache memory in parallel with storing the eviction data, further comprises transferring the fill data to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer.

19. The method of claim 14, wherein transferring the fill data to the first cache memory in parallel with storing the eviction data, further comprises transferring the fill data from the selected buffer to the first cache memory and concurrently transferring the eviction data into the selected buffer.

20. The method of claim 14, wherein the selected buffer is divided into a plurality of segments, the fill data is divided into a plurality of portions, one of the portions of the fill data is stored in each of the segments, the eviction data is divided into a plurality of portions, and the method further comprises:

transferring a first portion of the fill data stored in a first segment to the first cache memory;

storing a first portion of the eviction data in the first segment; and

repeating the transferring of remaining portions of the fill data and the storing of portions of the eviction data for the remaining segments.

21. A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a processor, comprising:

a first cache memory; and

a bus unit comprising a plurality of buffers and operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.