Software and Hardware Coordinated Prefetch

• US 20140189249A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Abandoned Application

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Ye, Handong, Hu, Ziang
• Application Number:
  US13/730,314
• Publication Number:
  US 20140189249A1
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Included is an apparatus comprising a processor configured to identify a code segment in a program, analyze the code segment to determine a memory access pattern, if the memory access pattern is regular, turn on hardware prefetching for the code segment by setting a control register before the code segment, and turn off the hardware prefetching by resetting the control register after the code segment. Also included is a method comprising identifying a code segment in a program, analyzing the code segment to determine a memory access pattern, if the memory access pattern is regular, turning on hardware prefetching for the code segment by setting a control register before the code segment, and turning off the hardware prefetching by resetting the control register after the code segment.

Claims

1. An apparatus comprising:

a processor configured to;

identify a code segment in a program;

analyze the code segment to determine a memory access pattern;

if the memory access pattern is regular,

turn on hardware prefetching for the code segment by setting a control register before the code segment; and

turn off the hardware prefetching by resetting the control register after the code segment.

2. The apparatus of claim 1, wherein the processor is further configured to:

determine a prefetching stride for the hardware prefetching if the memory access pattern is regular.

3. The apparatus of claim 2, wherein setting the control register before the code segment further indicates the prefetching stride.

4. The apparatus of claim 3, wherein the control register comprises a first bit and at least one additional bit, wherein an on state or an off state of the hardware prefetching is indicated by the first bit, and wherein the prefetching stride is indicated by the at least one additional bit.

5. The apparatus of claim 4, wherein the on state of the hardware prefetching is indicated by a binary ‘

1’

in the first bit, and wherein the off state of the hardware prefetching is indicated by a binary ‘

0’

in the first bit.

6. The apparatus of claim 2, wherein the code segment comprises a loop with at least one iteration.

7. The apparatus of claim 1, wherein the processor is further configured to:

translate the code segment to an executable code; and

execute the executable code, wherein if the memory access pattern is regular, executing the executable code comprises prefetching data from a memory to a cache without using any prefetching instruction.

8. The apparatus of claim 2, wherein the processor is further configured to:

if the memory access pattern is irregular,

insert at least one prefetching instruction into the code segment.

9. A method comprising:

identifying a code segment in a program;

analyzing the code segment to determine a memory access pattern;

if the memory access pattern is regular,

turning on hardware prefetching for the code segment by setting a control register before the code segment; and

turning off the hardware prefetching by resetting the control register after the code segment.

14. The method of claim 9, further comprising:

translating the code segment to an executable code; and

executing the executable code, wherein if the memory access pattern is regular, executing the executable code comprises prefetching data from a memory to a cache without using any prefetching instruction.

10. The method of claim, further comprising:

if the memory access pattern is regular,

determining a prefetching stride for the hardware prefetching.

11. The method of claim 10, wherein setting the control register before the code segment further indicates the prefetching stride.

12. The method of claim 11, wherein the control register comprises a first bit and at least one additional bit, wherein an on state or an off state of the hardware prefetching is indicated by the first bit, and wherein the prefetching stride is indicated by the at least one additional bit.

13. The method of claim 10, wherein the code segment comprises a loop with at least one iteration.

15. The method of claim 10, further comprising inserting at least one prefetching instruction into the code segment if the memory access pattern is irregular.

16. An apparatus comprising:

an on-chip register configured to indicate a state of hardware prefetching, wherein the on-chip register is controlled by a compiler.

17. The apparatus of claim 16, wherein the state of hardware prefetching comprises an on state, an off state, and a prefetching stride.

18. The apparatus of claim 17, wherein the control register comprises a first bit and at least one additional bit, wherein the on state and the off state is indicated by the first bit, and wherein the prefetching stride is indicated by the at least one additional bit.

19. The apparatus of claim 17, wherein the on state is indicated by a binary ‘

1’

in the first bit, and wherein the off state is indicated by a binary ‘

0’

in the first bit.

20. The apparatus of claim 16, wherein the state of hardware prefetching corresponds to a loop in a program, wherein no prefetching instruction is present inside the loop if the state of hardware prefetching is in the on state.