PROGRAMMABLE HARDWARE ACCELERATORS IN CPU

• US 20140189312A1
• Filed: 12/27/2012
• Published: 07/03/2014
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: TAN, Kia Leong
• Granted Patent: US 9,880,852 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4806 Task transfer initiation or dispatching
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram the programmable hardware accelerator to execute the first type of instructions, and transmit the first type of instructions to the programmable hardware accelerator to be executed.

Claims

1. A processing system comprising:

an instruction queue to store instructions to be executed by a processing execution block;

a programmable hardware accelerator; and

a controller programmed to;

monitor the instruction queue to detect a first type of instructions stored in the instruction queue,

reprogram the programmable hardware accelerator to execute the first type of instructions; and

transmit the first type of instructions to the programmable hardware accelerator to be executed.

2. The processing system of claim 1, wherein the controller is further programmed to:

detect a second type of instructions in the instruction queue,

reprogram the programmable hardware accelerator to execute the second type of instructions; and

transmit the second type of instructions to the programmable hardware accelerator to be executed.

3. The processing system of claim 1, wherein the programmable hardware accelerator is a field-programmable gate array.

4. The processing system of claim 2, wherein:

the first type of instructions comprise addition operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the addition operations; and

the second type of instructions comprise multiplication operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the multiplication operations.

5. The processing system of claim 1, wherein the programmable hardware accelerator is powered off when it is not executing instructions.

6. The processing system of claim 1, wherein the controller reprograms the programmable hardware accelerator to execute the first type of instructions only if the number of the first type of instructions in the queue is above a threshold.

7. The processing system of claim 1, further comprising:

a plurality of programmable hardware accelerators;

wherein

the controller is further programmed to selectively reprogram the plurality of programmable hardware accelerators to execute the first type of instructions.

8. The processing system of claim 8, wherein the controller is further programmed to:

in a first operation mode, power off the plurality of hardware accelerators,

in a second operation mode, power on a predetermined number of the plurality of hardware accelerators and power off the remaining hardware accelerators; and

in a third operation mode, power on the plurality of hardware accelerators.

9. The processing system of claim 8, wherein the controller is further programmed select a mode of operation based on the number of instructions to be executed by the plurality of hardware accelerators.

10. An apparatus comprising:

a processor to execute instructions stored in an instruction queue using a processing execution block, wherein the processor is configured to;

monitor, using a controller, the instruction queue to detect a first type of instructions stored in the instruction queue,

reprogram, using the controller, a programmable hardware accelerator to execute the first type of instructions; and

transmit, using the controller, the first type of instructions to the programmable hardware accelerator to be executed.

11. The apparatus of claim 10, wherein the controller is programmed to:

detect a second type of instructions stored in the instruction queue,

reprogram the programmable hardware accelerator to execute the second type of instructions; and

transmit the second type of instructions to the programmable hardware accelerator to be executed.

12. The apparatus of claim 10, wherein the programmable hardware accelerator is a field-programmable gate array.

13. The apparatus of claim 11, wherein:

the first type of instructions comprise addition operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the addition operations; and

the second type of instructions comprise multiplication operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the multiplication operations.

14. The processing apparatus of claim 10, wherein the programmable hardware accelerator is powered off when it is not executing instructions.

15. The apparatus of claim 10, wherein the controller reprograms the programmable hardware accelerator to execute the first type of instructions only if the number of the first type of instructions in the queue is above a threshold.

16. The apparatus of claim 10, further comprising:

a plurality of programmable hardware accelerators;

wherein

the controller is further programmed to selectively reprogram the plurality of programmable hardware accelerators to execute the first type of instructions.

17. The apparatus of claim 16, wherein the controller is further programmed to:

in a first operation mode, power off the plurality of hardware accelerators,

in a second operation mode, power on a predetermined number of the plurality of hardware accelerators and power off the remaining hardware accelerators; and

in a third operation mode, power on the plurality of hardware accelerators.

18. The apparatus of claim 16, wherein the controller is further programmed select a mode of operation based on the number of instructions to be executed by the plurality of hardware accelerators.

19. An apparatus comprising:

a processor to execute instructions stored in an instruction queue using a processing execution block,

a programmable hardware accelerator; and

a controller programmed to;

monitor the instruction queue to detect a first type of instructions stored in the instruction queue,

reprogram the programmable hardware accelerator to execute the first type of instructions; and

transmit the first type of instructions to the programmable hardware accelerator to be executed.

20. The apparatus of claim 19, wherein the controller is programmed to:

detect a second type of instructions stored in the instruction queue,

reprogram the programmable hardware accelerator to execute the second type of instructions; and

transmit the second type of instructions to the programmable hardware accelerator to be executed.

21. The apparatus of claim 19, wherein the programmable hardware accelerator is a field-programmable gate array.

22. The apparatus of claim 20, wherein:

the first type of instructions comprise addition operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the addition operations; and

the second type of instructions comprise multiplication operations and the controller is further programmed to reprogram the programmable hardware accelerator to execute the multiplication operations.

23. The apparatus of claim 19, wherein the programmable hardware accelerator is powered off when it is not executing instructions.

24. The apparatus of claim 19, wherein the controller reprograms the programmable hardware accelerator to execute the first type of instructions only if the number of the first type of instructions in the queue is above a threshold.

25. An method comprising:

monitoring instructions, stored in an instruction queue, to be executed by a processing execution block;

detecting a first type of instructions stored in the instruction queue,

reprogramming a programmable hardware accelerator to execute the first type of instructions; and

transmitting the first type of instructions to the programmable hardware accelerator to be executed.

26. The method of claim 25, further comprising:

detecting a second type of instructions stored in the instruction queue,

reprogramming the programmable hardware accelerator to execute the second type of instructions; and

transmitting the second type of instructions to the programmable hardware accelerator to be executed.

27. The method of claim 25, wherein the programmable hardware accelerator is a field-programmable gate array.

28. The method of claim 26, wherein:

the first type of instructions comprise addition operations and the programmable hardware accelerator is reprogrammed to execute addition operations; and

the second type of instructions comprise multiplication operations and the programmable hardware accelerator is reprogrammed to execute the multiplication operations.

29. The method of claim 25, wherein the programmable hardware accelerator is powered off when it is not executing instructions.

30. The method of claim 25, wherein the programmable hardware accelerator is reprogrammed to execute the first type of instructions only if the number of the first type of instructions in the queue is above a threshold.