INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY

• US 20140189368A1
• Filed: 12/29/2012
• Published: 07/03/2014
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert M., Gopal, Vinodh, Yap, Kirk S.
• Granted Patent: US 8,924,741 B2
• Time in Patent Office: Days
• US Class Current: 713/190
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Claims

1. A processor comprising:

a decode stage to decode a first instruction for a SIMD secure hashing algorithm round slice, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and

one or more execution units, responsive to the decoded first instruction, to;

perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set; and

store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1, wherein the first instruction specifies said SIMD destination register as a destination operand.

3. The processor of claim 2, wherein the first instruction specifies said SIMD destination register also as the source data operand set.

4. The processor of claim 1, wherein the first instruction specifies said rotator set portion of rotate settings by a first field in an immediate operand.

5. The processor of claim 4, wherein the first instruction specifies said round-slice portion of the secure hashing algorithm round by a second field in the immediate operand.

6. The processor of claim 5, wherein said secure hashing algorithm comprises:

an MD5 algorithm.

7. The processor of claim 5, wherein said secure hashing algorithm comprises:

a SHA-1 algorithm.

8. The processor of claim 5, wherein said secure hashing algorithm comprises:

a SHA-2 algorithm.

9. The processor of claim 1, wherein the message-plus-constant operand set has a message-plus-constant sum for each iteration of the set of round iterations.

10. A processor comprising:

a vector register comprising a plurality of m data fields to store values of m data elements;

a decode stage to decode a first instruction for executing a hash-round-slice of a hash algorithm, the hash-round-slice having a plurality of iterations less that a total number of round iterations of the hash algorithm, the first instruction specifying;

an input state source operand specifying the vector register, an immediate operand, and a message/constant combinations operand; and

an execution unit coupled with the register file, and responsive to the decoded first instruction, to receive the input state and the message/constant combinations, and to generate an output state for each iteration of the plurality of iterations, said execution unit comprising;

a multiplexer to select a message/constant combination from the message/constant combinations operand according to an iteration count of the plurality of iterations;

one or more functional blocks to perform logical combinations of a portion of the m data elements of the input state source operand according to a hash round type specified by the first instruction;

one or more adders to sum at least one or more input state value, the selected message/constant combination, and a portion of logical combinations output from said one or more functional blocks;

an output state latch to store an output state generated as a result of an iteration; and

a bypass from the output state latch to bypass the output state to the input state for each next iteration of the plurality of iterations.

11. The processor of claim 10, wherein the first instruction also specifies said vector register as an output state destination operand.

12. The processor of claim 10, said execution unit further comprising:

a rotator to perform a bitwise rotate according to a rotation value of a rotate set specified by the first instruction.

13. The processor of claim 12, wherein the first instruction specifies said rotate set by a first field in the immediate operand.

14. The processor of claim 13, wherein the first instruction specifies said hash round type by a second field in the immediate operand.

15. The processor of claim 14, wherein the first instruction specifies said hash round type as one of four MD5 round types.

16. The processor of claim 14, wherein the first instruction specifies said hash round type as one of three SHA-1 round types.

17. The processor of claim 14, wherein the first instruction specifies said hash round type as a SHA-2 round type.

18. The processor of claim 10, wherein the message/constant combinations operand has a message/constant combination for each iteration of the plurality of iterations.

19. The processor of claim 18, wherein the message/constant combinations comprise sums of a message data element plus a respective constant data element for each iteration of the plurality of iterations, stored in a portion of the m data fields of a second vector register.

20. A method comprising:

storing in a first portion of a plurality of m data fields of a first vector register, an input state source operand of a hash algorithm;

storing in a second portion of the plurality of m data fields of a second vector register, a message-plus-constant operand set of the hash algorithm;

executing, in a processor, a SIMD instruction for a hash-round-slice having a plurality of iterations less that a total number of round iterations of the hash algorithm; and

for each iteration of the hash-round-slice, generating a result of an iteration, storing an output state generated as the result of the iteration, and bypassing the output state to the input state for each next iteration of the plurality of iterations.

21. The method of claim 20 further comprising:

for each iteration of the hash-round-slice, selecting a message-plus-constant of an iteration from the message-plus-constant operand set, processing a portion of the input state according to a round type specified by the SIMD instruction, and adding the selected message-plus-constant to the processed portion of the input state.

22. The method of claim 21 further comprising:

for each iteration of the hash-round-slice, performing a bitwise rotate, according to a rotation value of a rotate set specified by the SIMD instruction, of the sum from adding the selected message-plus-constant to the processed portion of the input state.

23. The method of claim 22 wherein the SIMD instruction specifies said round type as one of four MD5 round types.

24. The method of claim 21 further comprising:

for each iteration of the hash-round-slice, performing a bitwise rotate, according to a first rotation value of a rotate set specified by the SIMD instruction, of a first portion of the input state to generate a first rotated value;

performing a bitwise rotate, according to a second rotation value of a rotate set specified by the SIMD instruction, of a second portion of the input state to generate a second rotated value; and

adding the first rotated value to the sum from adding the selected message-plus-constant to the processed portion of the input state.

25. The method of claim 24 wherein the SIMD instruction specifies said round type as one of three SHA-1 round types.

26. The method of claim 21 wherein the SIMD instruction specifies said round type by a first field in an immediate operand.

27. The method of claim 26 wherein the SIMD instruction specifies a rotate set by a second field in the immediate operand.

28. The method of claim 21 wherein the SIMD instruction specifies said round type as a SHA-2 round type.

31. The method of claim 26 wherein the SIMD instruction specifies said rotator set portion of rotate settings by a second field in the immediate operand.

29. A processing system comprising:

a memory to store a first instruction for a SIMD secure hashing algorithm round slice; and

a processor comprising;

an instruction fetch stage to fetch the first instruction;

a decode stage to decode the first instruction, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and

an execution stage, responsive to the decoded first instruction, to;

perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set; and

store a result of the first instruction in a SIMD destination register.

30. The processing system of claim 29, wherein the first instruction specifies said round-slice portion of the secure hashing algorithm round by a first field in an immediate operand.