LIVE ERROR RECOVERY

• US 20140189427A1
• Filed: 05/13/2013
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brown, Alexander, Das Sharma, Debendra, Jayaprakash Bharadwaj, Prahladachar, Thaliyil, Junaid
• Granted Patent: US 9,262,270 B2
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Claims

1. An apparatus comprising:

receiver logic to identify a packet at a port of a serial data link;

error logic to;

identify a packet at a port of a serial data link;

determine that the packet is associated with an error;

initiate entry into an error recovery mode based on the determination that the packet is associated with the error, wherein entry into the error recovery mode is to cause the serial data link to be forced down.

2. The apparatus of claim 1, wherein forcing the data link down causes all subsequent inbound packets to be dropped.

3. The apparatus of claim 2, wherein forcing the data link down further causes all pending outbound requests and completions to be aborted.

4. The apparatus of claim 3, wherein the error logic is further to generate and send a master abort completion for one of the aborted completions.

5. The apparatus of claim 1, wherein the error logic is further to drop the packet.

6. The apparatus of claim 1, wherein the error is at least one of a group comprising:

a transaction layer packet error, a flow control protocol error, and a data link layer protocol error.

7. The apparatus of claim 1, wherein the error logic is further to determine that the error is one of a set of errors that is to trigger the error recovery mode.

8. The apparatus of claim 7, wherein the set of errors is identifiable from an error mask register corresponding to the error recovery mode.

9. The apparatus of claim 8, wherein the set of errors is further included in errors identified as uncorrectable errors by another error mask.

10. The apparatus of claim 1, wherein entering the error recovery mode includes entering a disable state.

11. The apparatus of claim 1, wherein the error is associated with an uncorrectable severity and the error logic is further to force association of the error with a correctable severity.

12. The apparatus of claim 11, wherein the error logic is further to cause the error to be corrected.

13. The apparatus of claim 1, wherein the error logic is further to identify that all transactions on the data link have been dropped and identify that all error registers for the data link have been cleared.

14. The apparatus of claim 13, wherein the error logic is to determine that the transactions have been dropped based on a quisced control bit value of a register.

15. The apparatus of claim 13, wherein the error logic is to clear an error recovery bit of a status control register corresponding to the data link based on identifying that all transactions on the data link have been dropped and that all error registers for the data link have been cleared.

16. The apparatus of claim 15, wherein the error logic is further to initiate retraining of the link based on the clearing of the error recovery bit, wherein the error recovery bit indicates whether error recovery mode is active.

17. The apparatus of claim 1, wherein entry into the error recovery mode is to be initiated on a same clock cycle as detection of the error.

18. An apparatus comprising:

interface logic to interface with a serial data link;

receiver logic to receive a packet; and

error logic to;

determine that the packet is associated with an error; and

initiate entry into an error recovery mode based on the determination that the packet is associated with the error, wherein entry into the error recovery mode is to cause interface logic to drop an inbound packet and abort an outbound request.

19. The apparatus of claim 18, wherein the interface logic is to abort all pending outbound requests and completions during error recovery mode.

20. The apparatus of claim 18, wherein the interface logic is to drop all inbound packets during error recovery mode.

21. An apparatus comprising:

error logic, comprising transaction layer logic, data link layer logic, and physical layer logic, wherein the error logic is to;

detect a particular error associated with a particular packet;

determine, based on a first register value, that the particular error is to be designated as an uncorrectable error;

determine, based on a second register value, that the particular error is to trigger an error recovery mode, wherein the error recovery mode is to cause inbound and outbound packets subsequent to the particular error to be dropped;

determine from a third register value whether the error recovery mode is enabled; and

service the particular error based at least in part on the first, second, and third register values.

22. The apparatus of claim 21, wherein the error logic is further to initiate the error recovery mode based on a determination that the third register value indicates that the error recovery mode is enabled, and initiating the error recover mode includes asserting an error recovery status control bit of a register.

23. The apparatus of claim 22, wherein the error logic is further to:

identify that the error recovery status control bit is cleared; and

initiate reactivation of the data link based on the clearing of the error recovery status control bit.

24. A method comprising:

identifying a packet at a port of a serial data link;

determining that the packet is associated with an error; and

initiating entry into an error recovery mode based on the determination that the packet is associated with the error, wherein entry into the error recovery mode is to cause the serial data link to be forced down.

25. The method of claim 24, further comprising forcing down the serial data link, wherein forcing down the data link includes:

entering a recovery state; and

transitioning from the recovery state to a disabled state.

26. The method of claim 25, wherein forcing down the data link includes sending a sequence of training sequences, and the training sequences include a hit indicating an attempted entry into the disabled state.

27. The method of claim 24, wherein the error is designated an uncorrectable error, the method further comprising causing the error to be designated as a correctable error, wherein the error causes a correctable error interrupt.

28. The method claim 24, wherein the packet is an outbound packet to be sent to another device over the data link.

29. The method claim 24, wherein the packet is an inbound packet received from another device over the data link.

30. A system comprising:

a first device;

a second device to be communicatively coupled to the first device over an interconnect, the second device comprising error logic executable to;

identify a packet at a port of a serial data link of the interconnect;

determine that the packet is associated with an error;

initiate an error recovery mode on the port based on the determination that the packet is associated with the error, wherein the error recovery mode is to contain the error to the port.

31. The system of claim 30, further comprising an error handler.

32. The system of claim 30, wherein the interconnect comprises a Peripheral Component Interconnect Express (PCIe)-compliant interconnect.

33. The system of claim 30, wherein the first device comprises a first microprocessor and the second device comprises a second microprocessor.