GLOBAL LOW POWER CAPTURE SCHEME FOR CORES
First Claim
1. A method for testing an integrated circuit, said method comprising:
- programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit;
counting a number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache; and
staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on a respective number of first clock signal pulses counted for each of the plurality of cores and the cache.
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Abstract
A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.
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Citations
19 Claims
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1. A method for testing an integrated circuit, said method comprising:
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programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit; counting a number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache; and staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on a respective number of first clock signal pulses counted for each of the plurality of cores and the cache. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for testing an integrated circuit, said method comprising:
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programming a respective duration of a first time window for each of a plurality of modules on the integrated circuit, wherein the modules comprise cores and a cache; counting a number of pulses of a first clock signal during the first time window for each of the plurality of modules; and dynamically staggering capture pulses to a first subset of modules by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of modules. - View Dependent Claims (10, 11)
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12. A system for testing an integrated circuit, said system comprising:
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a computer system comprising a tester processor, wherein said tester processor is communicatively coupled to a integrated circuit, wherein said integrated circuit comprises; a plurality of cores and a cache; an I/O port operable to program a respective duration of a first time window for each of the plurality of cores and the cache on the integrated circuit; and a plurality of fast clock generating modules configured to; count a number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache; and stagger capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein a number of pulses generated is based on a respective number of first clock signal pulses counted for each of the plurality of cores and the cache. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification