FAILURE RATE BASED CONTROL OF PROCESSORS

• US 20140189696A1
• Filed: 12/28/2012
• Published: 07/03/2014
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Daniel Sanchez Pedreno, Nicholas Axelos
• Inventors: Vera, Xavier, Ramirez, Tanausu, Abellanas, Enric H., Axelos, Nicholas, Casado, Javier C., Pedreo, Daniel Sanchez
• Granted Patent: US 9,619,309 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80

Abstract

A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.

Claims

1. A method comprising:

determining a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of a plurality of tasks; and

enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration.

2. The method of claim 1, further comprising specifying the different maximum failure rates.

3. The method of claim 1, wherein determining comprises determining a minimum operational voltage for each of the different maximum failure rates, and wherein enforcing comprises enforcing each of the logic to operate at or above the corresponding minimum operational voltage.

4. The method of claim 3, wherein determining comprises determining the minimum operational voltages based on at least one derating factor selected from temperature, altitude, Architectural Vulnerability Factor (AVF), a timing derating factor, a logic derating factor, and combinations thereof.

5. The method of claim 3, wherein determining comprises:

determining a higher minimum operational voltage for a lower maximum failure rate assigned to a first task having supervisory control over a second task; and

determining a lower minimum operational voltage for a higher maximum failure rate assigned to the second task.

6. The method of claim 5, wherein the first task comprises an operating system task and the second task comprises a non-operating system task.

7. The method of claim 5, wherein the first task comprises a main thread and the second task comprises a sub-thread of the main thread.

8. The method of claim 5, wherein the first task comprises a time-critical task and the second task comprises a non-time critical task.

9. The method of claim 1, wherein determining comprises determining different configurations of error correction code for the different maximum failure rates, and wherein enforcing comprises enforcing the logic to operate with the different configurations of the error correction code.

10. The method of claim 1, further comprising enforcing a global failure rate including:

estimating a failure rate for each of the tasks;

combining the estimated failure rates into a combined failure rate;

comparing the combined failure rate with the global failure rate;

determining that the combined failure rate is not less than the global failure rate; and

taking at least one action to reduce the combined failure rate.

11. The method of claim 10, wherein taking the at least one action comprises de-activating at least one of the logic.

12. The method of claim 10, wherein taking the at least one action comprises increasing at least one minimum operational voltage for at least one corresponding task.

13. The method of claim 1, wherein determining comprises determining at least three different minimum operational voltages each for one of at least three different maximum failure rates.

14. The method of claim 1, wherein enforcing comprises enforcing at least ten cores, each executing a different task of at least ten tasks, to operate at or above a corresponding determined minimum operational voltage.

15. A processor comprising:

a plurality of logical processors to each execute a different corresponding task of a plurality of tasks;

logic to determine a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of the plurality of tasks; and

logic to enforce the plurality of logical processors to operate according to the different corresponding determined operational configurations when executing the corresponding tasks.

16. The processor of claim 15, wherein the logic to determine the different operational configurations comprises logic to determine a minimum operational voltage for each of the different maximum failure rates, and wherein the logic to enforce comprises logic to enforce each of the logical processors to operate at or above the corresponding minimum operational voltage.

17. The processor of claim 16, wherein the logic to determine the minimum operational voltages comprises logic to determine the minimum operational voltages based on at least one derating factor selected from temperature, altitude, Architectural Vulnerability Factor (AVF), a timing derating factor, a logic derating factor, and combinations thereof.

18. The processor of claim 16, wherein the logic to determine the different operational configurations comprises logic to determine a higher minimum operational voltage for a lower maximum failure rate corresponding to a first task having supervisory control over a second task and determine a lower minimum operational voltage for a higher maximum failure rate corresponding to the second task.

19. The processor of claim 18, wherein the first task comprises an operating system task and the second task comprises a non-operating system task.

20. The processor of claim 18, wherein the first task comprises a main thread and the second task comprises a sub-thread of the main thread.

21. The processor of claim 18, wherein the first task comprises a time-critical task and the second task comprises a non-time critical task.

22. The processor of claim 15, wherein the logic to determine the different operational configurations comprises logic to determine different configurations of error correction code for the different maximum failure rates.

23. The processor of claim 15, further comprising global failure rate enforcement logic to:

estimate a failure rate for each of the tasks;

combine the estimated failure rates into a combined failure rate;

compare the combined failure rate with the global failure rate;

determine that the combined failure rate is not less than the global failure rate; and

take at least one action to reduce the combined failure rate.

24. A system comprising:

an interconnect;

a processor coupled with the interconnect, the processor including;

a plurality of logical processors to each execute a different corresponding task of a plurality of tasks;

logic to determine a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of the plurality of tasks; and

logic to enforce the plurality of logical processors to operate according to the different corresponding determined operational configurations when executing the corresponding tasks; and

a dynamic random access memory (DRAM) coupled with the interconnect.

25. The system of claim 24, wherein the logic to determine the different operational configurations comprises logic to determine a minimum operational voltage for each of the different maximum failure rates based on at least one derating factor selected from temperature, altitude, Architectural Vulnerability Factor (AVF), a timing derating factor, a logic derating factor, and combinations thereof.

26. The system of claim 24, wherein the logic to determine the different operational configurations comprises logic to determine different configurations of logic that affect failure rates.