FAILURE RATE BASED CONTROL OF PROCESSORS
First Claim
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1. A method comprising:
- determining a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of a plurality of tasks; and
enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration.
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Abstract
A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.
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Citations
26 Claims
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1. A method comprising:
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determining a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of a plurality of tasks; and enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A processor comprising:
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a plurality of logical processors to each execute a different corresponding task of a plurality of tasks; logic to determine a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of the plurality of tasks; and logic to enforce the plurality of logical processors to operate according to the different corresponding determined operational configurations when executing the corresponding tasks. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A system comprising:
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an interconnect; a processor coupled with the interconnect, the processor including; a plurality of logical processors to each execute a different corresponding task of a plurality of tasks; logic to determine a different operational configuration for each of a plurality of different maximum failure rates, each of the different maximum failure rates corresponding to a different task of the plurality of tasks; and logic to enforce the plurality of logical processors to operate according to the different corresponding determined operational configurations when executing the corresponding tasks; and a dynamic random access memory (DRAM) coupled with the interconnect. - View Dependent Claims (25, 26)
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Specification