METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR

• US 20140191178A1
• Filed: 01/08/2014
• Published: 07/10/2014
• Est. Priority Date: 01/08/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Boivin, Philippe
• Granted Patent: US 9,196,654 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

Claims

1. A method, comprising:

forming a vertical MOS transistor, the forming of the MOS transistor including;

forming, above a semiconductor surface, a dielectric layer, a conductive layer in the dielectric layer;

etching a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface;

forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the portion of the semiconductor surface;

forming an etch-protection semiconductor sidewall on a lateral edge of the hole, the sidewall covering the gate dielectric and an outer region of the bottom dielectric, leaving an inner region of the bottom dielectric exposed;

etching the exposed inner region of the bottom dielectric until the semiconductor surface is reached; and

depositing a semiconductor material in the hole.

2. The method according to claim 1, further comprising forming, in the semiconductor surface, a doped region including dopants of a first conductivity type.

3. The method according to claim 2, further comprising forming a conduction terminal of the transistor by diffusing the dopants from the doped region into the semiconductor material in the hole.

4. The method according to claim 2 wherein the forming of the transistor further includes doping the etch-protection semiconductor sidewall with dopants of a second conductivity type.

5. The method according to claim 1, further comprising:

implanting dopants into the top surface of the semiconductor material; and

diffusing the dopants into the hole to form a conduction terminal of the transistor.

6. The method according to claim 1, further comprising, after forming the gate dielectric:

forming a charge storage layer covering the gate dielectric; and

forming a tunnel dielectric layer covering the charge storage layer.

7. A transistor, comprising:

a substrate;

a first dielectric on the substrate;

a conductive layer in the first dielectric ;

a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of a surface of the substrate;

a gate dielectric on the inner lateral edge of the conductive layer;

a first semiconductor material in the hole;

an etch-protection semiconductor sidewall on a lateral edge of the hole, between the gate dielectric and the first semiconductor material; and

a bottom dielectric having an outer region between a bottom of the etch-protection sidewall and the surface.

8. The transistor according to claim 7, further comprising a region in the surface including dopants of a first conductivity type.

9. The transistor according to claim 8 wherein the etch-protection semiconductor sidewall is a second semiconductor material including dopants of a second conductivity type.

10. The transistor according to claim 7, further comprising a charge storage layer and a tunnel dielectric layer between the gate dielectric and the etch-protection sidewall.

11. A device, comprising:

a substrate;

a first doped layer in the substrate;

a first dielectric layer on the first doped layer;

a second dielectric layer on the first dielectric layer;

a conductive layer in the second dielectric layer;

a third dielectric layer on the second dielectric layer and on the conductive layer;

an opening through the third dielectric layer, the conductive layer, and the first dielectric layer, the opening exposing a surface of the first doped layer, sidewalls of the opening including portions of the first and third dielectric layer and the conductive layer;

a first dielectric region at an intersection of the surface of the first doped layer and a first sidewall of the opening;

a second dielectric region at an intersection of the surface of the first doped layer and a first sidewall of the opening;

a third dielectric region on the portion of the sidewall that is the conducive layer;

a protective sidewall in the opening and on the first, second, and third dielectric regions;

a semiconductor material in the opening in contact with the surface of the first doped layer, the material having a first dopant concentration adjacent to the first doped layer and a second dopant concentration spaced from the first dopant concentration by the third dielectric region.

12. The device of claim 11, further comprising a charge storage layer in the opening adjacent to the third region and separated from the semiconductor material by the protective sidewall.

13. The device of claim 12, further comprising an dielectric layer between the charge storage layer and the protective sidewall.

14. The device of claim 11 wherein the semiconductor material includes a first portion in the opening and a second portion on top of the opening that is wider than the first portion in the opening.

15. The device of claim 14, further comprising a storage element formed on top of the second portion of the semiconductor material.

16. The device of claim 15 wherein the storage element includes a first electrode on the second portion of the semiconductor material, a resistive memory region on the first electrode, and a second electrode on the resistive memory region.