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METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR

  • US 20140191178A1
  • Filed: 01/08/2014
  • Published: 07/10/2014
  • Est. Priority Date: 01/08/2013
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • forming a vertical MOS transistor, the forming of the MOS transistor including;

    forming, above a semiconductor surface, a dielectric layer, a conductive layer in the dielectric layer;

    etching a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface;

    forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the portion of the semiconductor surface;

    forming an etch-protection semiconductor sidewall on a lateral edge of the hole, the sidewall covering the gate dielectric and an outer region of the bottom dielectric, leaving an inner region of the bottom dielectric exposed;

    etching the exposed inner region of the bottom dielectric until the semiconductor surface is reached; and

    depositing a semiconductor material in the hole.

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