Offloading Tessellation from a Graphics Processor to a Central Processing Unit

• US 20140192051A1
• Filed: 03/30/2012
• Published: 07/10/2014
• Est. Priority Date: 03/30/2012
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Meiri, Etay
• Application Number:
  US13/992,731
• Publication Number:
  US 20140192051A1
• Time in Patent Office: Days
• US Class Current: 345/423
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation

Abstract

In accordance with some embodiments, tessellation may be implemented in part on a central processing unit and in part on a graphics processing unit. The part that may be performed on a central processing unit may be a pre-computation stage in which the possible combinations of vertex stitching are computed and stored as a bit mask in a bidirectional array. Then, at run time, the graphics processor runs through the vertices as pre-computed in the central processing unit, in some embodiments.

Claims

1. A method comprising:

prior to tessellation, generating and storing possible stitching combinations.

2. The method of claim 1 including generating a number of stitching combinations in one processor and performing the tessellation in another processor.

3. The method of claim 2 including generating the number of stitching combinations in a central processing unit.

4. The method of claim 3 including performing the tessellation in a graphics processing unit.

5. The method of claim 4 including using only 65 external vertices and 63 interval vertices for a triangle to be tessellated.

6. The method of claim 5 including limiting the number of combinations to 4095 stitching combinations.

7. A method comprising:

obtaining pre-computed stitching combinations in a bit mask;

determining whether to proceed to the next vertex via an internal edge of a triangle or an external edge based on the bit mask; and

tessellating the triangle using the stitching combinations.

8. The method of claim 7 including proceeding through internal and external edges until a center of the triangle to be tessellated is obtained and then handling the center based on whether the center is one of a quad in the form of two triangles, an inwardly facing triangle, an outwardly facing triangle, or a null center.

9. The method of claim 7 including accessing a bidirectional array providing all possible stitching combinations.

10. At least one machine readable medium comprising a plurality of instructions and, in response to being executed on a computing device, causing the computing device to carry out a method comprising:

prior to tessellation, generating and storing possible stitching combinations.

25. The medium of claim 10 further storing instructions to carry out a method including generating a number of stitching combinations in one processor and performing the tessellation in another processor.

26. The medium of claim 25 further storing instructions to carry out a method including generating the number of stitching combinations in a central processing unit.

27. The medium of claim 26 further storing instructions to carry out a method including performing the tessellation in a graphics processing unit.

28. The medium of claim 27 further storing instructions to carry out a method including using only 65 external vertices and 63 interval vertices for a triangle to be tessellated.

29. The medium of claim 28 further storing instructions to carry out a method including limiting the number of combinations to 4095 stitching combinations.

11. An apparatus comprising:

a processor to process graphics by generating and storing possible stitching combinations prior to tessellation; and

a memory coupled to said processor.

12. The apparatus of claim 11 wherein said processor is a central processing unit.

13. The apparatus of claim 11 wherein said processor is a graphics processing unit.

14. The apparatus of claim 11 including at least two processors, one processor to generate the number of stitching combinations and the other processor to perform the tessellation.

15. The apparatus of claim 14 wherein said processor to generate the number of stitching combinations is a central processing unit.

16. The apparatus of claim 15 wherein said processor to perform the tessellation is a graphics processing unit.

17. The apparatus of claim 16 wherein said central processing unit uses only 65 external vertices and 63 internal vertices for a triangle to be tessellated.

18. The apparatus of claim 17, said central processing unit to limit the number of combinations to 4095 stitching combinations.

19. An apparatus comprising:

a processor to obtain pre-computed stitching combinations in a bit mask, determine whether to proceed to the next vertex via an internal edge of a triangle or an external edge based on the bit mask and tessellate the triangle using stitching combinations; and

a memory coupled to said processor.

20. The apparatus of claim 19, said processor to process internal and external edges until a center of a triangle to be tessellated is obtained and then handle the center based on whether the center is one of a quad in the form of two triangles, an inwardly facing triangle, an outwardly facing triangle, or a null center.

21. The apparatus of claim 19, said processor to access a bidirectional array providing all possible stitching combinations.

22. The apparatus of claims 19 including an operating system.

23. The apparatus of claims 19 including a battery.

24. The apparatus of claims 19 including firmware and a module to update said firmware