SYSTEM AND METHOD FOR PROVIDING POWER SAVINGS IN A PROCESSOR ENVIRONMENT

• US 20140195835A1
• Filed: 01/04/2013
• Published: 07/10/2014
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Song, Ting Lok, Teoh, Poh Thiam, Chin, Jennifer, Gan, Say Cheong, Lim, Sujea, Lim, Su Wei, E., Sun Zheng
• Granted Patent: US 9,563,256 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

Claims

1. A method for reducing power consumption in a processing environment, comprising:

powering down a root port;

initiating a first downstream cycle by a central processing unit (CPU) to the root port;

identifying a power up activity for the CPU; and

triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port.

2. The method of claim 1, wherein the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion.

3. The method of claim 1, wherein a prewake indicator is sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

4. The method of claim 1, wherein the root port is associated with a Peripheral Component Interconnect Express (PCIe) port.

5. The method of claim 1, further comprising:

receiving the second downstream cycle; and

sending the second downstream cycle to a device.

6. The method of claim 1, wherein the CPU is coupled to a plurality of high-speed serial input/output (I/O) ports.

7. The method of claim 1, wherein the power state is associated with a PCIe root port Idle Power state.

8. An apparatus for reducing power consumption in a processing environment, comprising:

a central processing unit (CPU); and

a root port configured to be powering down, wherein the CPU is configured to initiate a first downstream cycle to the root port and to receive a power up indicator, and wherein an exit flow is to be triggered for a power state in conjunction with sending a second downstream cycle to the root port.

9. The apparatus of claim 8, wherein the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion.

10. The apparatus of claim 8, wherein a prewake indicator is sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

11. The apparatus of claim 8, wherein the root port is associated with a Peripheral Component Interconnect Express (PCIe) port.

12. The apparatus of claim 8, wherein the second downstream cycle is sent to a device.

13. The apparatus of claim 8, wherein the CPU is coupled to a plurality of high-speed serial input/output (I/O) ports.

14. A method for reducing power consumption in a processing environment, comprising:

identifying a power management state associated with a central processing unit (CPU);

applying a power down state through a common mode turn off;

applying a transmit (Tx) common mode disable pin to a physical layer (PHY) in order to change a power state level associated with the CPU.

15. The method of claim 14, wherein the common mode disable pin is de-asserted to enable the Tx common mode.

16. The method of claim 14, further comprising:

receiving a status signal at an input/output (I/O) controller to indicate a power state level.

17. The method of claim 14, wherein the power management state is a selected one of a group of states, the group consisting of:

a) a link disable state;

b) a runtime state;

c) a detect state; and

d) an unconfigured lanes state.

18. The method of claim 14, wherein the Tx common mode is not turned off until a signal is received.

19. The method of claim 14, wherein the PHY allows a root port to exit to a power state level by returning a status signal.

20. The method of claim 14, further comprising:

sampling the pin in order to determine when to turn off the Tx common mode.

21. An apparatus for reducing power consumption in a processing environment, comprising:

a central processing unit (CPU); and

a root port coupled to the CPU, wherein a power management state associated with a central processing unit (CPU) is identified, and wherein a power down state is applied through a common mode turn off, and wherein a transmit (Tx) common mode disable pin is applied to a physical layer (PHY) in order to change a power state level associated with the CPU.

22. The apparatus of claim 21, wherein the common mode disable pin is de-asserted to enable the Tx common mode.

23. The apparatus of claim 21, wherein the power management state is a selected one of a group of states, the group consisting of:

a) a link disable state;

b) a runtime state;

c) a detect state; and

d) an unconfigured lanes state.

24. The apparatus of claim 21, wherein the PHY allows the root port to exit to a power state level by returning a status signal.

25. The apparatus of claim 21, wherein the pin is sampled in order to determine when to turn off the Tx common mode.