FinFET Device and Method of Fabricating Same

• US 20140197458A1
• Filed: 09/03/2013
• Published: 07/17/2014
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Wang, Chao-Hsiung, Liu, Chi-Wen, Huang, Jiun-Jia
• Granted Patent: US 9,859,429 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and

a fin structure comprising;

a silicon fin higher than top surfaces of the isolation regions;

a germanium-containing semiconductor region overlapped by the silicon fin;

silicon oxide regions on opposite sides of the germanium-containing semiconductor region; and

a first germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

2. The integrated circuit structure of claim 1, wherein the silicon oxide regions are separated from each other by the germanium-containing semiconductor region.

3. The integrated circuit structure of claim 1, wherein the silicon oxide regions are portions of a continuous silicon oxide region, and wherein the continuous silicon oxide region further comprises portions overlying and underlying the germanium-containing semiconductor region.

4. The integrated circuit structure of claim 3, wherein one of the germanium-containing semiconductor region and the first germanium-containing semiconductor layer is a substantially pure germanium region.

5. The integrated circuit structure of claim 1 further comprises:

a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions, and wherein the silicon strip is overlapped by the germanium-containing semiconductor region, portions of the silicon oxide regions, and portions of the first germanium-containing semiconductor layer; and

a second germanium-containing semiconductor layer between and in contact with the silicon strip and one of the silicon oxide regions.

6. The integrated circuit structure of claim 1, wherein at least a portion of the silicon oxide regions is over the top surfaces of the isolation regions.

7. The integrated circuit structure of claim 1 further comprising:

a gate stack on sidewalls and a top surface of the silicon fin; and

source/drain regions on opposite sides of the silicon fin.

8. The integrated circuit structure of claim 7, wherein the gate stack is in contact with sidewalls of the silicon oxide regions.

9. An integrated circuit structure comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and

a fin structure comprising;

a silicon fin higher than top surfaces of the isolation regions;

a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions;

a germanium-containing semiconductor region between aligned to the silicon fin and the silicon strip;

a first and a second silicon oxide region on opposite sides of the germanium-containing semiconductor region;

a first germanium-containing semiconductor layer between and in contact with the silicon fin and the first silicon oxide region;

a second germanium-containing semiconductor layer between and in contact with the silicon fin and the second silicon oxide region;

a third germanium-containing semiconductor layer between and in contact with the silicon strip and the first silicon oxide region; and

a fourth germanium-containing semiconductor layer between and in contact with the silicon strip and the second silicon oxide region.

10. The integrated circuit structure of claim 9, wherein the germanium-containing semiconductor region has a gradient germanium percentage, with inner portions of the germanium-containing semiconductor region having lower germanium percentages than respective outer portions.

11. The integrated circuit structure of claim 9, wherein at least a portion of the first silicon oxide region is over the top surfaces of the isolation region.

12. The integrated circuit structure of claim 9, wherein the silicon fin and the silicon strip are free from germanium.

13. The integrated circuit structure of claim 9, wherein each of the first and the second oxide regions comprises a portion not overlapped by the silicon fin.

14. The integrated circuit structure of claim 9, wherein the first and the second oxide regions are fully disconnected from each other.

15. The integrated circuit structure of claim 9 further comprising:

a gate stack on sidewalls and a top surface of the silicon fin; and

source/drain regions on opposite sides of the silicon fin.

16. The integrated circuit structure of claim 15, wherein the gate stack is in contact with sidewalls of the first and the second silicon oxide regions.

17. An integrated circuit structure comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and

a fin structure comprising;

a silicon fin higher than top surfaces of the isolation regions;

a germanium-containing semiconductor region; and

a silicon oxide region comprising;

a first and a second portion on opposite sides of the germanium-containing semiconductor region; and

a top portion connecting the first portion to the second portion, wherein the top portion fully separates the germanium-containing semiconductor region from the silicon fin.

18. The integrated circuit structure of claim 17 further comprising:

a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions;

a bottom portion of the silicon oxide region connecting the first portion to the second portion of the oxide region, wherein the bottom portion fully separates the germanium-containing semiconductor region from the silicon strip; and

a germanium-containing semiconductor layer between and in contact with the silicon strip and the bottom portion of the silicon oxide region.

19. The integrated circuit structure of claim 17 further comprising:

a germanium-containing semiconductor layer between and in contact with the silicon fin and the top portion of the silicon oxide region.

20. The integrated circuit structure of claim 17, wherein the germanium-containing semiconductor region is formed of substantially pure germanium.