SELF TESTING FAULT CIRCUIT APPARATUS AND METHOD

• US 20140197856A1
• Filed: 09/18/2013
• Published: 07/17/2014
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Leviton Manufacturing Company Incorporated
• Original Assignee: Leviton Manufacturing Company Incorporated
• Inventors: OSTROVSKY, Michael, KEVELOS, Adam
• Granted Patent: US 9,709,626 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: H02H 3/335 the main function being self testing of the device

Abstract

A process for self testing a fault circuit includes disabling an actuator, performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a hall cycle of a second polarity, and determining whether the self test was successful.

Claims

1-34. -34. (canceled)

35. A process for self testing a fault circuit comprising:

a) disabling an actuator;

b) performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity; and

c) determining whether the self test was successful.

36. The process as in claim 35, wherein said step of disabling said actuator comprises preventing a signal from reaching said actuator.

37. The process as in claim 36, wherein said step of disabling said actuator comprises blocking a SCR from receiving a fault signal.

38. The process as in claim 35, wherein said step of performing a self test comprises creating a current imbalance between a phase and neutral line.

39. The process as in claim 35, wherein said step of performing a self test comprises:

creating a current imbalance by activating at least one transistor to cause current to flow from at least one electrical conductor configured to be read by at least one fault sensor, wherein said current imbalance is read by said at least one fault sensor.

40. The process as in claim 35, wherein said step of performing a self test comprises:

a) detecting a zero crossing of an AC line signal;

b) timing a self test to occur during at least a portion of a first half polarity and during at least a portion of a second half cycle of opposite polarity.

41. The process as in claim 40, further comprising the step of timing a self test during an alternate half cycle of alternating current.

42. The process as in claim 41, wherein said step of timing a self test during at least one half cycle of alternating current comprises timing a self test during only a portion of said at least one half cycle of alternating current.

43. The process as in claim 35, further comprising the step of controlling a duration of a self test.

44. The process as in claim 43, wherein said step of controlling a duration of a self test comprises controlling said duration based upon an amount of power fed into a capacitor.

45. The process as in claim 44, wherein said step of controlling a duration of a self test comprises controlling a discharge rate of power of said capacitor.

46. The process as in claim 35, wherein said step of detecting a fault includes receiving a signal from a fault sensor indicating the presence of a fault.

47. The process as in claim 35, wherein said step of indicating a result of said self test comprises providing a light indication for said self test.

48. The process as in claim 35, wherein said step of indicating a result of said self test comprises providing an audio indication for said self test.

49. The process as in claim 35, wherein said step of indicating a result of said self test comprises indicating whether a self test is performed successfully.

50. The process as in claim 35, wherein said step of indicating a result c said self test comprises indicating whether a set of contacts have tripped.

51. The process as in claim 35, further comprising the step of determining an overcurrent condition.

52. The process as in claim 35, further comprising the step of determining overvoltage condition.

53. The process as in claim 35, further comprising the step of permanently removing the fault circuit from operation by opening a fusable link along at least one of said phase line and said neutral line.

54. The process as in claim 43, further comprising the step of controlling a duration of the self test based upon the presence of an external fault.

55. The process as in claim 54, wherein said step of controlling the duration of the self test comprises receiving an external fault comprising a ground fault.

56. The process as in claim 55, wherein said step of controlling a duration of a self test comprises removing power from a capacitor.

57. The process as in claim 56, wherein said step of receiving an external fault comprises providing power from said external fault to said capacitor to reduce a time for completing said step of performing a self test.

58. The process as in claim 56, further comprising the step of actuating an actuator to remove power to a load side when an external fault exists beyond said step of providing a self test.

59. The process as in claim 43, further comprising the step of determining when a fault signal is received to determine whether an external fault is occurring.

60. The process as in claim 59, further comprising the step of actuating said actuator to remove power to a load side in response to determining that an external fault exists.

61. The process as in claim 43, further comprising the step activating a transistor to control the duration of a self test.

62. The process as in claim 61, wherein said step of activating a transistor, comprises turning a transistor on, and wherein the process further includes the step of discharging a capacitor, wherein said step of turning a transistor on, creates a discharge path for said capacitor, to create a shorter test cycle.

63. The process as in claim 62, wherein after said step of discharging a capacitor is completed, said step of disabling an actuator is completed.

64-70. -70. (canceled)

71. A method for testing a fault circuit comprising the following steps:

a) periodically preventing an actuator from activating;

b) activating a self test by creating a current imbalance, which occurs across at least two different half cycles of opposite polarity;

c) testing a fault circuit by reading said current imbalance.

72-74. -74. (canceled)

75. A method for testing a fault circuit comprising:

periodically outputting a circuit hinder signal to hinder a disconnect signal from a fault detector circuit, the circuit hinder signal being output at a first period of time;

outputting a test signal to said fault detector circuit only if the circuit hinder signal is output, the test signal testing said fault detector circuit;

receiving from said fault detector circuit an output signal in response to the test signal when said fault detector is operative; and

activating an alarm during a second period of time if the output signal is not received during said first period of time.

76-77. -77. (canceled)