DOMAIN PROTECTION AND VIRTUALIZATION FOR SATA

• US 20140201481A1
• Filed: 01/16/2013
• Published: 07/17/2014
• Est. Priority Date: 01/16/2013
• Status: Active Grant

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Sathe, Satish, Chudgar, Keyur, Marulkar, Rajendra Sadananad
• Granted Patent: US 9,424,205 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/16 Protection against loss of memory contents contains no material, see G06F11/00
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 21/80 in storage media based on magnetic or optical technology, e.g. disks with sectors preventing unauthorised reproduction or copying of disc-type recordable media G11B20/00
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine

Abstract

Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs.

Claims

1. A system, comprising:

a memory configured for storing a data structure associated with a guest device;

a coprocessor, communicably coupled to the memory, configured for interfacing between the guest device and a SATA controller; and

a bus fabric configured for redirecting a SATA controller access from the guest device to a corresponding address in the data structure, wherein the coprocessor is further configured for performing an address translation for the access and forwarding the translated access via the bus fabric to the SATA controller.

2. The system of claim 1, wherein the bus fabric allows a SATA controller access originating from the coprocessor to proceed.

3. The system of claim 1, further comprising a memory management unit configured for storing address translation tables, and linking a physical address to a corresponding virtual address and an intermediate physical address.

4. The system of claim 3, wherein the memory management unit is configured for receiving memory accesses from the SATA controller and diverting the memory accesses to a physical address corresponding to an appropriate virtual address.

5. The system of claim 1, further comprising a queue manager configured for receiving command header requests from the guest device and storing them in a queue.

6. The system of claim 5, wherein the coprocessor is configured for translating addresses and forwarding the accesses to the SATA controller in an order that is based on the queue in the queue manager.

7. The system of claim 1, wherein the memory is at least one of DDR memory or on-chip memory.

8. The system of claim 1, wherein the coprocessor is configured for building a consolidated data structure in the memory based on data structures associated with a plurality of guest devices.

9. The system of claim 5, wherein the command header requests are associated with a source domain ID that identifies the guest device from which each command header request originated.

10. The system of claim 9, wherein the SATA controller is configured for checking whether the command header request has access permission based on the source domain ID, and is further configured for generating an error notification in response to request lacking permission.

11. The system of claim 7, wherein in response to the guest device storing the data structure in DDR memory, the coprocessor is configured for copying a portion of the data structure to the on-chip memory.

12. A method, comprising:

storing an advanced host controller interface data structure in a memory, wherein the data structure is associated with a guest operating system;

redirecting a SATA controller access to the data structure in response to the SATA controller access originating from the guest operating system;

translating an address for the access; and

forwarding the translated access via a bus fabric to the SATA controller.

13. The method of claim 12, further comprising:

receiving an access from the SATA controller; and

translating an address of the access to a physical address that corresponds to a specific virtual address.

14. The method of claim 12, further comprising receiving a command header request from the guest operating system and storing the command header request in a queue.

15. The method of claim 14, further comprising translating addresses of a plurality of accesses and forwarding the plurality of accesses to the SATA controller in an order based on the queue.

16. The method of claim 12, further comprising building a consolidated data structure in the memory based on data structures associated with a plurality of guest operating systems.

17. The method of claim 14, identifying the guest operating system the command header request originated from based on a source domain ID associated with the command header request.

18. The method of claim 17, further comprising:

determining whether the command header request has access permission based on the source domain ID;

executing the command in response to the command header request having permission; and

generating an error in response to the command header request not having permission.

19. The method of claim 12, further comprising copying a subset of the of the data structure to on-chip memory in response to the data structure being stored in DDR memory.

20. A system, comprising:

means for redirecting accesses from a plurality of guest devices to a SATA controller to a designated on-chip memory address;

means for queuing the accesses and determining permissions based on source domain IDs associated with the accesses; and

means for translating the accesses from a virtual address to a physical address and forwarding the accesses to the SATA controller.