METHOD AND APPARATUS FOR USING DYNAMIC VOLTAGE AND FREQUENCY SCALING WITH CIRCUIT-DELAY BASED INTEGRATED CIRCUIT IDENTIFICATION

• US 20140201851A1
• Filed: 01/16/2013
• Published: 07/17/2014
• Est. Priority Date: 01/16/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: GUO, Xu, SHEN, Liangguo
• Granted Patent: US 9,015,500 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

One feature pertains to a method that includes implementing a Physical Unclonable Function (PUF) circuit, and obtaining a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively. A second set of output bits is then obtained by operating the PUF circuit at the second supply voltage level and/or the second frequency, where the second set of output bits is in part different than the first set. Secure data is generated using the first set of output bits and the second sets of output bits.

Claims

1. A method operational within an electronic device, comprising:

implementing a Physical Unclonable Function (PUF) circuit;

obtaining a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency;

changing at least one of the first supply voltage level to a second supply voltage level and/or the first frequency to a second frequency, the second supply voltage level different than the first supply voltage level and the second frequency different than the first frequency;

obtaining a second set of output bits by operating the PUF circuit at the second supply voltage level and/or the second frequency, the second set of output bits at least in part different than the first set of output bits; and

generating secure data using at least a portion of the first set of output bits and at least a portion of the second set of output bits.

2. The method of claim 1, further comprising:

obtaining the first set of output bits and the second set of output bits in response to a same input challenge to the PUF circuit.

3. The method of claim 2, further comprising:

receiving the input challenge at the PUF circuit from a processing circuit.

4. The method of claim 1, wherein the secure data is generated by concatenating at least the portion of the first set of output bits and the portion of the second set of output bits.

5. The method of claim 1, wherein the secure data is generated using a cryptographic function based on at least the portion of the first set of output bits and the portion of the second set of output bits.

6. The method of claim 1, further comprising:

reducing a circuit area occupied by the PUF circuit by varying at least one of an input supply voltage of the PUF circuit and/or an input frequency of the PUF circuit.

7. The method of claim 6, wherein at least a portion of the circuit area is reduced by a factor N, the factor N equal to a number of different supply voltage and/or frequency level steps the PUF circuit is adapted to operate at.

8. The method of claim 7, wherein the portion of the circuit area reduced is a circuit-delay based sample generation module.

9. The method of claim 7, wherein the portion of the circuit area reduced is a number of delay paths.

10. The method of claim 1, wherein the PUF circuit is a circuit-delay based PUF circuit.

11. The method of claim 10, wherein the PUF circuit is one of a ring oscillator based PUF circuit, an arbiter PUF circuit, or a delay-path analysis based PUF circuit.

12. The method of claim 11, wherein the PUF circuit is the ring oscillator based PUF circuit, and the method further comprises:

selecting at least a pair of ring oscillators from a plurality of ring oscillators to obtain the first set of output bits;

changing the first supply voltage level of the PUF circuit to the second supply voltage level; and

selecting the pair of ring oscillators to obtain the second set of output bits.

13. The method of claim 11, wherein the PUF circuit is the arbiter PUF circuit, and the method further comprises:

selecting a circuit delay path from a plurality of circuit delay paths to obtain the first set of output bits;

changing the first supply voltage level of the PUF circuit to the second supply voltage level; and

selecting the circuit delay path to obtain the second set of output bits.

14. The method of claim 1, further comprising:

increasing the PUF circuit'"'"'s sensitivity to semiconductor-level manufacturing variation to increase entropy of the PUF circuit.

15. The method of claim 14, wherein increasing the PUF circuit'"'"'s sensitivity to semiconductor-level manufacturing variation includes:

reducing a power level consumed by the PUF circuit by changing at least one of the first supply voltage level of the PUF circuit to the second supply voltage level and/or the first frequency to the second frequency, wherein the second supply voltage level is less than the first supply voltage level and the second frequency is lower than the first frequency.

16. An electronic device, comprising:

a Physical Unclonable Function (PUF) circuit; and

a processing circuit communicatively coupled to the PUF circuit, the processing circuit adapted to

obtain a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency,

change at least one of the first supply voltage level to a second supply voltage level and/or the first frequency to a second frequency, the second supply voltage level different than the first supply voltage level and the second frequency different than the first frequency,

obtain a second set of output bits by operating the PUF circuit at the second supply voltage level and/or the second frequency, the second set of output bits at least in part different than the first set of output bits, and

generate secure data using at least a portion of the first set of output bits and at least a portion of the second set of output bits.

17. The electronic device of claim 16, wherein the processing circuit is further adapted to:

obtain the first set of output bits and the second set of output bits in response to a same input challenge to the PUF circuit.

18. The electronic device of claim 16, wherein a circuit area occupied by the PUF circuit is reduced by varying at least one of an input supply voltage of the PUF circuit and/or an input frequency of the PUF circuit.

19. The electronic device of claim 18, wherein at least a portion of the circuit area is reduced by a factor N, the factor N equal to a number of different supply voltage and/or frequency level steps the PUF circuit is adapted to operate at.

20. The electronic device of claim 16, wherein the PUF circuit is one of a ring oscillator based PUF circuit, an arbiter PUF circuit, or a delay-path analysis based PUF circuit.

21. The electronic device of claim 20, wherein the PUF circuit is the ring oscillator based PUF circuit, and the processing circuit is further adapted to:

select at least a pair of ring oscillators from a plurality of ring oscillators to obtain the first set of output bits;

change the first supply voltage level of the PUF circuit to the second supply voltage level; and

select the pair of ring oscillators to obtain the second set of output bits.

22. The electronic device of claim 16, wherein the processing circuit is further adapted to:

increase the PUF circuit'"'"'s sensitivity to semiconductor-level manufacturing variation to increase entropy of the PUF circuit.

23. The electronic device of claim 22, wherein the processor further adapted to increase the PUF circuit'"'"'s sensitivity to semiconductor-level manufacturing variation includes:

reduce a power level consumed by the PUF circuit by changing at least one of the first supply voltage level of the PUF circuit to the second supply voltage level and/or the first frequency to the second frequency, wherein the second supply voltage level is less than the first supply voltage level and the second frequency is lower than the first frequency.

24. An electronic device, comprising:

means for implementing a Physical Unclonable Function (PUF);

means for obtaining a first set of output bits from the means for implementing the PUF by operating the means for implementing the PUF at a first supply voltage level and/or first frequency;

means for changing at least one of the first supply voltage level to a second supply voltage level and/or the first frequency to a second frequency, the second supply voltage level different than the first supply voltage level and the second frequency different than the first frequency;

means for obtaining a second set of output bits by operating the means for implementing the PUF at the second supply voltage level and/or the second frequency, the second set of output bits at least in part different than the first set of output bits; and

means for generating secure data using at least a portion of the first set of output bits and at least a portion of the second set of output bits.

25. The electronic device of claim 24, further comprising:

means for obtaining the first set of output bits and the second set of output bits in response to a same input challenge to the means for implementing the PUF.

26. The electronic device of claim 24, wherein a circuit area occupied by the means for implementing the PUF is reduced by varying at least one of an input supply voltage of the means for implementing the PUF and/or an input frequency of the means for implementing the PUF.

27. The electronic device of claim 26, wherein at least a portion of the circuit area is reduced by a factor N, the factor N equal to a number of different supply voltage and/or frequency level steps the means for implementing the PUF is adapted to operate at.

28. The electronic device of claim 24, wherein the means for implementing the PUF is one of a ring oscillator based PUF circuit, an arbiter PUF circuit, or a delay-path analysis based PUF circuit.

29. The electronic device of claim 24, further comprising:

means for increasing the means for implementing the PUF'"'"'s sensitivity to semiconductor-level manufacturing variation to increase entropy of the means for implementing the PUF.

30. The electronic device of claim 29, wherein the means for increasing the means for implementing the PUF'"'"'s sensitivity to semiconductor-level manufacturing variation includes:

means for reducing a power level consumed by the means for implementing the PUF by changing at least one of the first supply voltage level of the means for implementing the PUF to the second supply voltage level and/or the first frequency to the second frequency, wherein the second supply voltage level is less than the first supply voltage level and the second frequency is lower than the first frequency.

31. A computer-readable storage medium having one or more instructions stored thereon, which when executed by at least one processor causes the processor to:

implement a Physical Unclonable Function (PUF);

obtain a first set of output bits from the PUF by operating the PUF at a first supply voltage level and/or first frequency;

change at least one of the first supply voltage level to a second supply voltage level and/or the first frequency to a second frequency, the second supply voltage level different than the first supply voltage level and the second frequency different than the first frequency;

obtain a second set of output bits by operating the PUF at the second supply voltage level and/or the second frequency, the second set of output bits at least in part different than the first set of output bits; and

generate secure data using at least a portion of the first set of output bits and at least a portion of the second set of output bits.

32. The computer-readable storage medium of claim 31, having additional instructions, which when executed by the processor cause the processor to further:

obtain the first set of output bits and the second set of output bits in response to a same input challenge to the PUF.