Wire-Last Integration Method and Structure for III-V Nanowire Devices

• US 20140203290A1
• Filed: 08/15/2013
• Published: 07/24/2014
• Est. Priority Date: 01/19/2013
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Josephine B., Lauer, Isaac, Sleight, Jeffrey W., Majumdar, Amlan
• Application Number:
  US13/967,953
• Publication Number:
  US 20140203290A1
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Claims

1. A nanowire FET device, comprising:

at least one fin formed on a wafer, wherein the fin comprises (i) portions having a layer of a III-V semiconductor material on an SOI layer which serve as source and drain regions of the device, and (ii) portions of the III-V semiconductor material released from the fin which serve as a nanowire channel of the device;

a gap filler material surrounding the fin; and

at least one gate, formed within a trench in the gap filler material, that surrounds the nanowire channel in a gate all around configuration.

2. The device of claim 1, wherein the SOI layer comprises silicon germanium.

3. The device of claim 1, wherein the III-V semiconductor material comprises at least one group III element and at least one group V element.

4. The device of claim 1, wherein the III-V semiconductor material is selected from the group consisting of:

aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide and combinations comprising at least one of the foregoing materials.

5. The device of claim 1, wherein the III-V semiconductor material comprises an epitaxial III-V semiconductor material.

6. The device of claim 1, wherein the gap filler material comprises a dielectric material.

7. The device of claim 1, wherein the nanowire channel has a length of from about 10 nm to about 50 nm.