Non-volatile Memory Cell Having A Floating Gate And A Coupling Gate With Improved Coupling Ratio Therebetween

• US 20140203343A1
• Filed: 07/16/2012
• Published: 07/24/2014
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Zhang, Yi, Lu, Wen-Juei, Wang, Chunming, Qiao, Baowei, Zhang, Zufa, Wang, Shiuh Luen
• Granted Patent: US 9,379,255 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.

Claims

1. A non-volatile memory cell comprising:

a semiconductor substrate of a first conductivity type having a top surface;

a first region of a second conductivity type in said substrate along the top surface;

a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;

a channel region between the first region and the second region;

a word line gate positioned over a first portion of the channel region, immediately adjacent to the first region, said word line gate spaced apart from the channel region by a first insulating layer;

a floating gate positioned over another portion of the channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface;

said floating gate having a first side wall adjacent to but separated from the word line gate; and

a second side wall opposite the first side wall, wherein said upper surface having a non-planar contour from said first side wall to said second side wall;

a coupling gate positioned over the upper surface of the floating gate and insulated therefrom by a third insulating layer, said coupling gate having a lower surface that has a contour that follows the contour of said upper surface of said floating gate; and

an erase gate positioned adjacent to the second side wall of the floating gate;

said erase gate positioned over the second region and insulated therefrom.

2. The memory cell of claim 1 wherein said upper surface of said floating gate has a step like non-planar contour.

3. The memory cell of claim 2 wherein said erase gate overhangs a portion of said floating gate.

4. The memory cell of claim 2 wherein said first side wall is taller than said second side wall.

5. The memory cell of claim 2 wherein said second side wall is taller than said first side wall.

7. The array of claim 5 wherein said second region extends in the row direction across a plurality of columns.

8. The array of claim 7 wherein said upper surface of each of said floating gates has a step like non-planar contour.

9. The array of claim 8 wherein said erase gate overhangs a portion of each of said plurality of floating gates.

10. The array of claim 8 wherein said first side wall of each floating gate is taller than said second side wall of each of said floating gate.

11. The array of claim 8 wherein said second side wall of each floating gate is taller than said first side wall of each floating gate.

6. An array of non-volatile memory cells comprising:

a semiconductor substrate of a first conductivity type having a top surface;

a plurality of memory cells arranged in an array with a plurality of rows and a plurality of columns;

each of said memory cells comprising a first region of a second conductivity type in said substrate along the top surface;

a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region in a column direction, with a channel region between the first region and the second region, each of said channel region having a first portion and a second portion, with the first portion immediately adjacent to the first region;

a word line gate, extending in a row direction perpendicular to the column direction, positioned over a plurality of the first portion of channel regions, said word line gate spaced apart from each channel region by a first insulating layer;

a floating gate positioned over the second portion of each channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface;

said floating gate having a first side wall adjacent to but separated from the word line gate; and

a second side wall opposite the first side wall, wherein said upper surface having a non-planar contour from said first side wall to said second side wall;

a coupling gate, extending in the row direction, positioned over the upper surface of a plurality of floating gates and insulated therefrom by a third insulating layer, said coupling gate having a lower surface that has a contour that follows the contour of said upper surface of said floating gate; and

an erase gate, extending in the row direction across a plurality of columns and positioned adjacent to the second side wall of a plurality of floating gates;

said erase gate positioned over the second region and insulated therefrom.

12. A non-volatile memory cell comprising:

a semiconductor substrate of a first conductivity type having a top surface;

a first region of a second conductivity type in said substrate along the top surface;

a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;

a channel region between the first region and the second region;

a word line gate positioned over a first portion of the channel region, immediately adjacent to the first region, said word line gate spaced apart from the channel region by a first insulating layer;

a floating gate positioned over another portion of the channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface;

said floating gate having a first side wall adjacent to but separated from the word line gate; and

a second side wall opposite the first side wall, wherein said upper surface having a non-planar contour from said first side wall to said second side wall;

a third insulating layer on said upper surface of said floating gate, said third insulating layer having a uniform thickness extending from said first side wall to said second side wall;

a coupling gate positioned over said third insulating layer; and

an erase gate positioned adjacent to the second side wall of the floating gate;

said erase gate positioned over the second region and insulated therefrom.

13. The memory cell of claim 12 wherein said upper surface of said floating gate has a step like non-planar contour.

14. The memory cell of claim 13 wherein said erase gate overhangs a portion of said floating gate.

15. The memory cell of claim 14 wherein said first side wall is taller than said second side wall.

16. The memory cell of claim 14 wherein said second side wall is taller than said first side wall.

17. A method of fabricating a non-volatile memory cell, said method comprising:

forming a first polysilicon layer on a first insulating layer on a semiconductor substrate, said first polysilicon layer having a top surface with a planar contour;

etching the top surface of said first polysilicon layer to produce a non-planar contour;

forming a second insulating layer on said top surface of said first polysilicon layer, with said second insulating layer substantially uniform in thickness over said top surface;

forming a second polysilicon layer on said second insulating layer, said second polysilicon layer having a bottom surface with a contour that substantially follows the non-planar contour of said top surface of said first polysilicon layer;

masking and cutting said second polysilicon layer, said second insulating layer, and said first polysilicon layer, to form a coupling gate and a floating gate, respectively;

forming a word line gate and an erase gate, on adjacent but respective opposite sides of said coupling gate and said floating gate;

forming source and drain regions in said substrate.

18. The method of claim 17 wherein said non-planar contour of said top surface of said first polysilicon layer has a step.

19. The method of claim 18 wherein said source is formed underneath the erase gate.

20. The method of claim 18, wherein said drain is formed adjacent to the word line gate.