SPIRAL METAL-ON-METAL (SMOM) CAPACITORS, AND RELATED SYSTEMS AND METHODS

• US 20140203404A1
• Filed: 01/21/2013
• Published: 07/24/2014
• Est. Priority Date: 01/21/2013
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Choi, Jihong, Zhu, John J., Chidambaram, PR, Yang, Bin, Ge, Lixin
• Application Number:
  US13/745,962
• Publication Number:
  US 20140203404A1
• Time in Patent Office: Days
• US Class Current: 257/534
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Claims

1. A multilayer metal-on-metal (MoM) capacitor disposed in a semiconductor die, the multilayer MoM capacitor comprising:

a first layer comprising;

a first electrode of the MoM capacitor coupled to a first trace, the first trace coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments; and

a second electrode of the MoM capacitor coupled to a second trace, the second trace coiled inside the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments; and

a second layer comprising;

the second electrode of the MoM capacitor coupled to a third trace, the third trace coiled in a second inwardly spiraling pattern; and

the first electrode of the MoM capacitor coupled to a fourth trace, the fourth trace coiled inside the second inwardly spiraling pattern.

2. The multilayer MoM capacitor of claim 1, wherein the second parallel trace segments are disposed substantially centered between the first parallel trace segments.

3. The multilayer MoM capacitor of claim 1, wherein the first and second parallel trace segments are substantially rectilinear.

4. The multilayer MoM capacitor of claim 1, wherein a spacing between the first parallel trace segments and the second parallel trace segments is less than approximately 40 nm.

5. The multilayer MOM capacitor of claim 1, further comprising a third layer comprising two inwardly spiraling conductive elements, a first inwardly spiraling conductive element electrically coupled to the first electrode and a second inwardly spiraling conductive element electrically coupled to the second electrode, wherein the first inwardly spiraling conductive element is exteriorly positioned relative to the second inwardly spiraling conductive element.

6. The multilayer MoM capacitor of claim 1, wherein the first trace and the fourth trace are coupled with a via positioned proximate a center of the first trace.

7. The multilayer MoM capacitor of claim 1 formed during a back end of line (BEOL) manufacturing process.

8. The multilayer MoM capacitor of claim 1, further comprising a device selected from the group consisting of:

a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which a MoM capacitor is integrated.

9. A multilayer metal-on-metal (MoM) capacitor disposed in a semiconductor die, the multilayer MoM capacitor comprising:

a first layer comprising;

a first electrode of the MoM capacitor coupled to a first conducting means, the first conducting means coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments; and

a second electrode of the MoM capacitor coupled to a second conducting means, the second conducting means coiled inside the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments; and

a second layer comprising;

the second electrode of the MoM capacitor coupled to a third conducting means, the third conducting means coiled in a second inwardly spiraling pattern; and

the first electrode of the MoM capacitor coupled to a fourth conducting means, the fourth conducting means coiled inside the second inwardly spiraling pattern.

10. The multilayer MoM capacitor of claim 9 wherein the first conducting means comprises a first trace.

11. The multilayer MoM capacitor of claim 9 wherein the second conducting means comprises a second trace.

12. A circuit in a semiconductor die comprising a multilayer MoM capacitor, the multilayer MoM capacitor comprising:

a first layer comprising;

a first electrode of the MoM capacitor coupled to a first trace, the first trace coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments; and

a second electrode of the MoM capacitor coupled to a second trace, the second trace coiled inside the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments; and

a second layer comprising;

the second electrode of the MoM capacitor coupled to a third trace, third trace coiled in a second inwardly spiraling pattern; and

the first electrode of the MoM capacitor coupled to a fourth trace, the fourth trace coiled inside the second inwardly spiraling pattern.

13. A method of forming a metal-on-metal (MoM) capacitor comprising:

providing a first mask for a semiconductor die, the first mask delimiting a first inwardly spiraling pattern;

positioning the first mask on a top layer of the semiconductor die;

depositing a first metal on the first mask to form a first electrode and a first trace of the MoM capacitor, the first trace formed in the inwardly spiraling pattern comprised of first parallel trace segments;

providing a second mask for the semiconductor die, the second mask delimiting a second inwardly spiraling pattern;

positioning the second mask on the top layer of the semiconductor die;

depositing a second metal on the second mask to form a second electrode and a second trace of the MoM capacitor, the second trace formed coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments.

14. The method of claim 13, wherein the first and second metals are the same and are conductive metals.

15. The method of claim 13, further comprising removing the first mask prior to positioning the second mask.

16. The method of claim 13, wherein depositing the second metal to form the second electrode and the second trace comprises disposing the second parallel trace segments substantially centered between the first parallel trace segments.

17. The method of claim 13, wherein providing the first mask comprises providing a first mask with a first substantially rectilinear inwardly spiraling pattern.

18. The method of claim 13, wherein a spacing between parallel trace segments is less than approximately 40 nm.

19. The method of claim 13, further comprising assembling a second layer of the MoM capacitor positioned above a plane defined by the first and second electrode.

20. The method of claim 19, wherein assembling the second layer comprises positioning spiral elements within one another in such a manner that elements electrically coupled to the first trace are inwardly positioned relative to elements electrically coupled to the second trace.