ELECTRONIC DEVICE PACKAGE AND PACKAGING SUBSTRATE FOR THE SAME

• US 20140203451A1
• Filed: 10/25/2013
• Published: 07/24/2014
• Est. Priority Date: 01/22/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SON, Min Young, KWON, Yong Min, MOON, Seo Hyun, IM, Sung Jun
• Granted Patent: US 9,059,149 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.

Claims

1. An electronic device package comprising:

a packaging substrate having first and second surfaces opposing one another, the packaging substrate including;

first and second electrode patterns formed on the first surface of the packaging substrate, and

first and second external terminals connected to the first and second electrode patterns,

the second electrode pattern being electrically insulated from the first electrode pattern and surrounding the first electrode pattern; and

an electronic device mounted on the first surface of the packaging substrate, the electronic device including;

first and second electrodes formed on a surface thereof facing the packaging substrate, and

the first and second electrodes being positioned on the first and second electrode patterns, respectively.

2. The electronic device package of claim 1, further comprising:

a first conductive via penetrating through the packaging substrate to connect the first electrode pattern to the first external terminal,

wherein the first external terminal is disposed on the second surface of the packaging substrate.

3. The electronic device package of claim 2, further comprising:

a second conductive via penetrating through the packaging substrate to connect the second electrode pattern to the second external terminal,

wherein the second external terminal is disposed on the second surface of the packaging substrate.

4. The electronic device package of claim 1, wherein the first electrode pattern includes a plurality of first electrode patterns separated from one another.

5. The electronic device package of claim 1, wherein the second electrode is separated from the first electrode and is provided to surround the first electrode.

6. The electronic device package of claim 5, wherein the second electrode pattern and the second electrode are bonded to one another and an internal space defined by a bonding region thereof is sealed.

7. The electronic device package of claim 1, wherein the second electrode is disposed around the first electrode and includes a plurality of second electrodes separated from one another.

8. The electronic device package of claim 7, wherein the plurality of second electrodes are symmetrically arranged based on the first electrode.

9. The electronic device package of claim 1, wherein the first and second electrodes of the electronic device have thicknesses less than those of the first and second electrode patterns.

10. The electronic device package of claim 1, wherein the electronic device is an optoelectronic device.

11. The electronic device package of claim 10, wherein a portion of the second electrode pattern is continuously exposed along edges of the electronic device.

12. A packaging substrate for an electronic device, the packaging substrate comprising:

a substrate body having first and second surfaces opposing one another;

a first electrode pattern disposed on the first surface of the substrate body;

a second electrode pattern disposed on the first surface of the substrate body, electrically insulated from the first electrode, and surrounding the first electrode pattern; and

first and second external terminals connected to the first and second electrode patterns, respectively.

13. The packaging substrate of claim 12, further comprising:

a first conductive via penetrating through the substrate body to connect the first electrode pattern to the first external terminal,

wherein the first external terminal is disposed on the second surface of the substrate body.

14. The packaging substrate of claim 13, further comprising:

a second conductive via penetrating through the substrate body to connect the second electrode pattern to the second external terminal,

wherein the second external terminal is disposed on the second surface of the substrate body.

15. The packaging substrate of claim 12, wherein the first electrode pattern includes a plurality of first electrode patterns separated from one another.

16-20. -20. (canceled)