Dynamic Adaptation of Continuous Time Linear Equalization Circuits
First Claim
1. A system comprising:
- a processor; and
an input/output (I/O) link, coupled to the processor, to compensate for process, voltage, and temperature (PVT) effects, the link including;
execution logic to determine first and second compensation codes; and
a driving circuit, coupled to the execution logic, to control impedance based on the first and second compensation codes;
wherein (a) the first code corresponds to a first variable resistance code for a variable resistive element, a first variable capacitance code for a variable capacitive element, and a first PVT condition; and
(b) the second code corresponds to a second variable resistance code for the variable resistive element, a second variable capacitance code for the variable capacitive element, and a second PVT condition unequal to the first PVT condition.
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Abstract
An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited to a Continuous Time Linear Equalization (CTLE) circuit. The PVT programming may be used to control gain peaking amplitude and gain peaking frequency across ranges of different PVTs. As a result, error performance is not impaired across different PVT corners and gain peaking is more consistent across different PVT corners. Other embodiments are included herein.
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Citations
25 Claims
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1. A system comprising:
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a processor; and an input/output (I/O) link, coupled to the processor, to compensate for process, voltage, and temperature (PVT) effects, the link including; execution logic to determine first and second compensation codes; and a driving circuit, coupled to the execution logic, to control impedance based on the first and second compensation codes; wherein (a) the first code corresponds to a first variable resistance code for a variable resistive element, a first variable capacitance code for a variable capacitive element, and a first PVT condition; and
(b) the second code corresponds to a second variable resistance code for the variable resistive element, a second variable capacitance code for the variable capacitive element, and a second PVT condition unequal to the first PVT condition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus comprising:
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control logic to determine first and second process, voltage, and temperature (PVT) conditions for an input/out (I/O) link and generate first and second impedance configurations based on the determined first and second PVT conditions; and driving logic, coupled to the control logic, to control impedance based on the first and second impedance configurations; wherein (a) the first impedance configuration corresponds to a first variable resistance setting for a variable resistive element, a first variable capacitance setting for a variable capacitive element, and the first PVT condition; and
(b) the second impedance configuration corresponds to a second variable resistance setting for the variable resistive element, a second variable capacitance setting for the variable capacitive element, and the second PVT condition that is unequal to the first PVT condition. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus comprising:
an input/output (I/O) module including a continuous time linear equalization (CTLE) circuit, wherein the I/O module is to; determine a first process, voltage, temperature (PVT) condition; and dynamically adjust a gain peaking frequency and a gain peaking amplitude for the CTLE circuit based on the first PVT condition. - View Dependent Claims (22, 23, 24, 25)
Specification