Dynamic Adaptation of Continuous Time Linear Equalization Circuits

• US 20140203839A1
• Filed: 01/21/2013
• Published: 07/24/2014
• Est. Priority Date: 01/21/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Subratakumar Mandal
• Inventors: MANDAL, SUBRATAKUMAR
• Granted Patent: US 8,872,541 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H04L 25/0288 the shape being matched to the transmission line pre-equalisation per se H04L25/03343
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited to a Continuous Time Linear Equalization (CTLE) circuit. The PVT programming may be used to control gain peaking amplitude and gain peaking frequency across ranges of different PVTs. As a result, error performance is not impaired across different PVT corners and gain peaking is more consistent across different PVT corners. Other embodiments are included herein.

Claims

1. A system comprising:

a processor; and

an input/output (I/O) link, coupled to the processor, to compensate for process, voltage, and temperature (PVT) effects, the link including;

execution logic to determine first and second compensation codes; and

a driving circuit, coupled to the execution logic, to control impedance based on the first and second compensation codes;

wherein (a) the first code corresponds to a first variable resistance code for a variable resistive element, a first variable capacitance code for a variable capacitive element, and a first PVT condition; and

(b) the second code corresponds to a second variable resistance code for the variable resistive element, a second variable capacitance code for the variable capacitive element, and a second PVT condition unequal to the first PVT condition.

2. The system of claim 1, wherein the first and second codes are to generate generally consistent gain peaking for both of the first and second PVT conditions.

3. The system of claim 2, wherein the first code corresponds to a first PVT corner and the second code corresponds to a second PVT corner.

4. The system of claim 1, the driving circuit comprising a Continuous Time Linear Equalization (CTLE) circuit including the variable resistive element and the variable capacitive element.

5. The system of claim 4, wherein the link includes a differential amplifier to receive impedance feedback based on the first and second PVT conditions and generate an output signal.

6. The system of claim 5, wherein the execution logic includes a counter coupled to the amplifier and is to select one of the first and second codes based on the output signal.

7. The system of claim 4, wherein the variable resistive element and the variable capacitive element are included in different stages of the CTLE circuit.

8. The system of claim 7, wherein the variable resistive element includes a variable resistor and the variable capacitive element includes a variable capacitor.

9. The system of claim 1, wherein the first and second variable resistance codes and the first and second variable capacitance codes are included in non-volatile memory coupled to the link.

10. The system of claim 1 wherein the link includes a Peripheral Component Interconnect Express (PCIe) based link.

11. The system of claim 1, wherein the first and second codes are to generate generally consistent gain peaking at data rates of at least 8 gigabytes per second for both of the first and second PVT conditions.

12. An apparatus comprising:

control logic to determine first and second process, voltage, and temperature (PVT) conditions for an input/out (I/O) link and generate first and second impedance configurations based on the determined first and second PVT conditions; and

driving logic, coupled to the control logic, to control impedance based on the first and second impedance configurations;

wherein (a) the first impedance configuration corresponds to a first variable resistance setting for a variable resistive element, a first variable capacitance setting for a variable capacitive element, and the first PVT condition; and

(b) the second impedance configuration corresponds to a second variable resistance setting for the variable resistive element, a second variable capacitance setting for the variable capacitive element, and the second PVT condition that is unequal to the first PVT condition.

13. The apparatus of claim 12, wherein the first and second impedance configurations are to generate generally consistent gain peaking for both of the first and second PVT conditions.

14. The apparatus of claim 13, wherein the first impedance configuration corresponds to a first PVT corner and the second impedance configuration corresponds to a second PVT corner.

15. The apparatus of claim 12, the driving logic comprising a Continuous Time Linear Equalization (CTLE) circuit including the variable resistive element and the variable capacitive element.

16. The apparatus of claim 15 comprising a differential amplifier to receive impedance feedback based on the first and second PVT conditions and generate an output signal.

17. The apparatus of claim 16, the control logic comprising a counter, coupled to the amplifier, to select one of the first and second impedance configurations based on the output signal.

18. The apparatus of claim 15, wherein the variable resistive element and the variable capacitive element are included in different stages of the CTLE circuit.

19. The apparatus of claim 18, wherein the variable resistive element includes a variable resistor and the variable capacitive element includes a variable capacitor.

20. The apparatus of claim 12, wherein the first impedance configuration is one of a setting included in a lookup table and a logic circuit configuration.

21. An apparatus comprising:

an input/output (I/O) module including a continuous time linear equalization (CTLE) circuit, wherein the I/O module is to;

determine a first process, voltage, temperature (PVT) condition; and

dynamically adjust a gain peaking frequency and a gain peaking amplitude for the CTLE circuit based on the first PVT condition.

22. The apparatus of claim 21, wherein the I/O module is to:

to determine first and second compensation codes; and

control impedance based on the first and second compensation codes;

wherein (a) the first code corresponds to a first variable resistance code for a variable resistive element included in the CTLE circuit, a first variable capacitance code for a variable capacitive element included in the CTLE circuit, and the first PVT condition; and

(b) the second code corresponds to a second variable resistance code for the variable resistive element, a second variable capacitance code for the variable capacitive element, and a second PVT condition unequal to the first PVT condition.

23. The apparatus of claim 22, wherein the first and second codes are to generate generally consistent gain peaking for both of the first and second PVT conditions.

24. The apparatus of claim 22, wherein the first code corresponds to a first PVT corner and the second code corresponds to a second PVT corner.

25. The apparatus of claim 22, wherein the first and second codes are to generate generally consistent gain peaking at data rates of at least 8 gigabytes per second for both of the first and second PVT conditions.