SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device comprising:
- a first transistor; and
a circuit including a second transistor,wherein a channel of the first transistor is included in an oxide semiconductor layer,wherein a first signal is input to one of a source and a drain of the first transistor,wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,wherein a first clock signal is input to the circuit,wherein a second clock signal is output from the circuit, andwherein a timing of the second clock signal is different from a timing of the first clock signal.
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Accused Products
Abstract
To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a first transistor; and a circuit including a second transistor, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to the circuit, wherein a second clock signal is output from the circuit, and wherein a timing of the second clock signal is different from a timing of the first clock signal. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a first transistor; and a second transistor, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to one of a source and a drain of the second transistor, wherein a second clock signal is output from the other of the source and the drain of the second transistor, and wherein a timing of the second clock signal is different from a timing of the first clock signal. - View Dependent Claims (6, 7, 8)
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9. A semiconductor device comprising:
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a first transistor; a second transistor; a first inverter; and a second inverter, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to one of a source and a drain of the second transistor through the first inverter, wherein a second clock signal is output from the other of the source and the drain of the second transistor through the second inverter, and wherein a timing of the second clock signal is different from a timing of the first clock signal. - View Dependent Claims (10, 11, 12)
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13. A semiconductor device comprising:
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a first transistor; a second transistor; a first inverter; a second inverter; and a capacitor, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to one of a source and a drain of the second transistor and to the second inverter through the first inverter, wherein the other of the source and the drain of the second transistor is electrically connected to one of electrodes of the capacitor, wherein a second clock signal is output from the second inverter, and wherein a timing of the second clock signal is different from a timing of the first clock signal. - View Dependent Claims (14, 15, 16)
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17. A semiconductor device comprising:
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a first transistor; a circuit including a second transistor; a flip-flop; and a logic circuit, wherein a channel of the first transistor is included in an oxide semiconductor layer, wherein an output of the logic circuit is input to a gate of the first transistor, wherein a first signal is input to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a first clock signal is input to the circuit, wherein a second clock signal is output from the circuit to the flip-flop, wherein a second signal and an output signal of the flip-flop are input to the logic circuit, and wherein a timing of the second clock signal is different from a timing of the first clock signal. - View Dependent Claims (18, 19, 20)
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Specification