MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DETECTING METHOD

• US 20140204655A1
• Filed: 03/26/2014
• Published: 07/24/2014
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Granted Patent: US 9,570,141 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 29/50016 of retention

Abstract

To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor.

Claims

1. (canceled)

2. A memory device comprising:

a cell array comprising a plurality of memory cells, at least one of the plurality of memory cells comprising;

a first capacitor;

a second capacitor; and

a transistor,

wherein one of a source electrode and a drain electrode of the transistor is directly connected to the first capacitor and the second capacitor,

wherein a capacitance of the first capacitor is larger than a capacitance of the second capacitor, and

wherein the transistor comprises an oxide semiconductor film.

3. The memory device according to claim 2, wherein the transistor comprises:

the source electrode and the drain electrode over the oxide semiconductor film;

a gate insulating film over the oxide semiconductor film; and

a gate electrode over the gate insulating film.

4. The memory device according to claim 2, wherein the source electrode and the drain electrode are provided on and in contact with the oxide semiconductor film.

5. The memory device according to claim 2, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

6. The memory device according to claim 2, wherein the oxide semiconductor film comprises a crystal.

7. The memory device according to claim 2, wherein the capacitance of the first capacitor is one thousand or more times a capacitance of the second capacitor.

8. The memory device according to claim 3, wherein the first capacitor comprises:

the one of the source electrode and the drain electrode of the transistor;

the gate insulating film over the one of the source electrode and the drain electrode of the transistor; and

a conductive film over the gate insulating film.

9. The memory device according to claim 3, wherein the second capacitor comprises:

the one of the source electrode and the drain electrode of the transistor;

the gate insulating film over the one of the source electrode and the drain electrode of the transistor;

an insulating film over the gate electrode of the transistor; and

a conductive film over the insulating film.

10. The memory device according to claim 3,

wherein the oxide semiconductor film comprises a first region between the gate electrode and the source electrode and a second region between the gate electrode and the drain electrode, and

wherein conductivities of the first region and the second region is higher than a conductivity of a channel formation region of the transistor between the first region of the second region.

11. The memory device according to claim 10,

wherein the first region and the second region comprise a dopant, and

wherein the dopant is Group 5.

12. The memory device according to claim 3, wherein the gate electrode overlaps with the source electrode and the drain electrode.

13. The memory device according to claim 2, comprising a driver circuit functionally connected to the cell array.

14. A memory device comprising:

a cell array comprising a plurality of memory cells, at least one of the plurality of memory cells comprising;

a first capacitor;

a second capacitor;

a first transistor; and

a second transistor,

wherein one of a source electrode and a drain electrode of the first transistor is directly connected to the first capacitor, the second capacitor, and a gate electrode of the second transistor,

wherein a capacitance of the first capacitor is larger than a capacitance of the second capacitor, and

wherein the first transistor comprises an oxide semiconductor film.

15. The memory device according to claim 14, wherein the first transistor comprises:

the source electrode and the drain electrode over the oxide semiconductor film;

a first gate insulating film over the oxide semiconductor film; and

a gate electrode over the first gate insulating film.

16. The memory device according to claim 14, wherein the source electrode and the drain electrode of the first transistor are provided on and in contact with the oxide semiconductor film.

17. The memory device according to claim 14, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

18. The memory device according to claim 14, wherein the oxide semiconductor film comprises a crystal.

19. The memory device according to claim 14, wherein the capacitance of the first capacitor is one thousand or more times a capacitance of the second capacitor.

20. The memory device according to claim 15, wherein the first capacitor comprises:

the one of the source electrode and the drain electrode of the first transistor;

the first gate insulating film over the one of the source and the drain of the first transistor; and

a conductive film over the first gate insulating film.

21. The memory device according to claim 15, wherein the second capacitor comprises:

the one of the source electrode and the drain electrode of the first transistor;

the first gate insulating film over the one of the source electrode and the drain electrode of the first transistor;

an insulating film over the gate electrode of the first transistor; and

a conductive film over the insulating film.

22. The memory device according to claim 15,

wherein the oxide semiconductor film comprises a first region between the gate electrode of the first transistor and the source electrode of the first transistor and a second region between the gate electrode of the first transistor and the drain electrode of the first transistor, and

wherein conductivities of the first region and the second region is higher than a conductivity of a channel formation region of the first transistor between the first region of the second region.

23. The memory device according to claim 22,

wherein the first region and the second region comprise a dopant, and

wherein the dopant is Group 5.

24. The memory device according to claim 15, wherein the gate electrode of the first transistor overlaps with the source electrode and the drain electrode of the first transistor.

25. The memory device according to claim 14, comprising a driver circuit functionally connected to the cell array.

26. The memory device according to claim 14,

wherein the first transistor is provided over the second transistor,

wherein the second transistor comprises:

a channel formation region;

a second gate insulating film over the channel formation region; and

the gate electrode over the second gate insulating film.

27. The memory device according to claim 26, wherein the one of the source electrode and the drain electrode of the first transistor is in direct contact with the gate electrode of the second transistor.

28. The memory device according to claim 26, wherein the channel formation region of the second transistor comprises any one of amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon.