System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache

• US 20140208005A1
• Filed: 11/05/2013
• Published: 07/24/2014
• Est. Priority Date: 01/22/2013
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Simionescu, Horia, Baderdinni, Anant, Bert, Luca
• Application Number:
  US14/071,702
• Publication Number:
  US 20140208005A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2211/1009 Cache, i.e. caches used in RAID system with parity
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information.

Claims

1. A method for operating a cache memory supported by solid-state data storage modules, the method comprising:

defining a layout for distributing data in a cache memory supported by N solid-state memory elements, where N is an integer;

initializing, in a cache controller, a line fill count and a write count;

receiving a data block in a cache interface, the contents of the data block designated for storage in the cache memory;

determining, in a cache controller, if the content of the data block is presently stored in a primary data store coupled to the cache interface or if the content is from a host system in anticipation of a subsequent transfer to the primary data store; and

when the content of the data block is presently stored in the primary data store,

storing the data block in the cache memory in response to the line fill count and incrementing the line fill count,

otherwise,

storing the data block in the cache memory in response to the write count and incrementing the write count.

2. The method of claim 1, wherein data stored in the cache memory is sequentially arranged in each respective solid-state module.

3. The method of claim 1, further comprising:

determining when the line fill count is N; and

incrementing a first stripe count and reinitializing the line fill count.

4. The method of claim 1, further comprising:

storing the N−

1^th data block;

determining when the write count is N−

1;

computing a parity block responsive to the N−

1 data blocks that have been received and stored in the cache memory but not transferred to the primary data store;

incrementing a second stripe count and reinitializing the write count; and

storing the parity block.

5. The method of claim 4, wherein storing the parity block includes locating the parity block in accordance with the layout and storing the N−

1^th data block includes locating the data block in the next available strip in the N^th solid-state data storage module.

6. The method of claim 4, further comprising:

receiving a subsequent data block in the cache interface; and

repeating the determining and storing steps of claim 1.

7. A data storage system, comprising:

a cache memory supported by N solid-state storage modules, where N is an integer; and

a controller coupled to the cache memory, the controller including processing logic that is configurable to define and manage data transfers to and from the cache memory, the data transfers as managed by the controller including successive line fill operations to designated solid-state storage devices distributed among the N solid-state storage elements in a defined manner.

8. The data storage system of claim 7, wherein data stored in the cache memory is sequentially arranged in each respective solid-state module.

9. The data storage system of claim 7, wherein the data stored in the cache is not exposed to host applications.

10. The data storage system of claim 7, wherein the N solid-state storage modules are logically divided into a first set of addressable strips.

11. The data storage system of claim 7, wherein N is an integer greater than two.

12. The data storage system of claim 7, wherein one of the N solid-state modules includes a strip designated to store parity information for a stripe.

13. The data storage system of claim 7, wherein the controller computes a parity block responsive to n−

1 write blocks that have been received and stored in the cache memory by performing an Exclusive-Or (XOR) operation on the n−

1 write blocks.

14. The data storage system of claim 7, wherein the N solid-state modules are coupled to the controller via dedicated interfaces.

15. The data storage system of claim 7, wherein the N solid-state modules are integrated on a printed circuit.

16. The data storage system of claim 7, wherein the data transfers further include write operations to a second set of addressable strips different from the first set of addressable strips.

17. The data storage system of claim 16, wherein parity information for a stripe of write operations is calculated only after buffered data present in the cache is greater than or equal to a capacity equivalent to an amount of data that can be stored in a full-stripe write operation.

18. A computer-readable medium having stored thereon, in computer executable non-transitory form, instructions that, when executed on a processing system of a data storage controller, direct the data storage controller to:

identify when a data block designated for storage in a cache memory, supported by N solid-state storage modules, where N is an integer, is presently stored in a primary data store coupled to the cache memory; and

when the content of the data block is presently stored in the primary data store,

locate the data block in the cache memory in response to a line fill count,

otherwise,

locate the data block in the cache memory in response to a write count, wherein each data block is placed in a defined logically sequential order within each respective solid-state storage module.

19. The computer-readable medium of claim 18, wherein the N solid-state storage modules are logically divided into respective sets of addressable strips designated for the receipt of cache line fill operations and the receipt of write block operations.

20. The computer-readable medium of claim 19, wherein the sets of addressable strips include a strip designated to store parity information for a stripe upon receipt of a N−

1^th data block with data responsive to write block operations.