MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS
First Claim
1. A computer system comprising:
- primary processing circuitry;
a bus coupled to the primary processing circuitry; and
memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry including;
at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry; and
computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit being configured for performing supplemental functions at least partially during time periods that are not accessing intervals.
1 Assignment
0 Petitions
Accused Products
Abstract
A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.
65 Citations
24 Claims
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1. A computer system comprising:
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primary processing circuitry; a bus coupled to the primary processing circuitry; and memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry including; at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry; and computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit being configured for performing supplemental functions at least partially during time periods that are not accessing intervals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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memory storage circuitry configured for interaction with a memory bus; and memory control circuitry co-integrated and co-located with memory storage circuitry, the memory control circuitry being configured for Restricted Cache Coherence Protocol. - View Dependent Claims (10, 11)
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12. A method of local computation in a memory device comprising:
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locally determining whether a memory line has been checked out for writing; upon determining that the memory line has not been checked out for writing, retrieving data from at least one location associated with the memory line; and performing a local action and/or computation involving the retrieved data. - View Dependent Claims (13, 14)
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15. A method of providing data to a memory bus comprising:
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retrieving in a first memory device a first data set; performing at the first memory device a first local action and/or computation involving the retrieved first data set; providing an indication directly to a second memory device coupled to the memory bus of a status of the first local action and/or computation; and performing a second local action and/or computation at the second memory device responsive to the provided indication. - View Dependent Claims (16)
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17. A method of performing a computation comprising:
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performing a local action and/or computation at a first memory device; and defining a retrieval strategy for the first memory device based on the local action and/or computation at a first memory device. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24-35. -35. (canceled)
Specification