POWER-UP RESTRICTION

• US 20140208135A1
• Filed: 01/18/2013
• Published: 07/24/2014
• Est. Priority Date: 01/18/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Keil, Shane J., de Cesare, Josh P., Machnicki, Erik P.
• Granted Patent: US 9,645,630 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken

Abstract

Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Claims

1. An apparatus, comprising:

a circuit; and

a power management unit configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state.

2. The apparatus of claim 1, further comprising:

a fabric configured to transmit the attempted communication to the circuit from a device, wherein the circuit is configured to exit the power-managed state in response to receiving the attempted communication; and

wherein the fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

3. The apparatus of claim 2, wherein the fabric is configured to reject the attempted communication in response to the power management unit indicating that the attempted communication is not permitted to cause the circuit to exit from the power-managed state.

4. The apparatus of claim 1, wherein the power management unit includes a register configured to store the programmable setting, and wherein the apparatus is configured to modify the programmable setting in response to the apparatus entering a power-managed state.

5. The apparatus of claim 4, wherein the power management unit is configured to clock gate the circuit in response to the apparatus entering a power-managed state, and wherein the register is configured to be accessible by a driver of the power management unit, wherein the driver is executable to set the programmable setting.

6. The apparatus of claim 1, wherein the apparatus is configured to:

receive, from a driver of the circuit, a request to permit the circuit to exit the power-managed state; and

adjust the programmable setting to permit the circuit to exit the power-managed state in response to an attempted communication with the circuit.

7. The apparatus of claim 1, wherein the apparatus is a telecommunication device, and wherein the apparatus is configured to cause the circuit to enter the power-managed stage in response to determining that the apparatus is to enter a low-power mode.

8. An apparatus, comprising:

a fabric configured to facilitate communication between a plurality of devices including a first device, wherein the first device is configured to awaken from a power-managed state in response to receiving a communication via the fabric; and

wherein the fabric is configured to examine a programmable setting in response to an attempted communication with the first device, wherein the programmable setting indicates whether the first device is permitted to be awakened.

9. The apparatus of claim 8, wherein the fabric is configured to read the programmable setting from a register, wherein the register is within a power management unit configured to provide power to the first device.

10. The apparatus of claim 9, wherein in response to the register indicating that a circuit may not be accessed, the fabric is configured to return an error in response to a request to access the first device.

11. The apparatus of claim 9, wherein the fabric is configured to transmit an indication to the power management unit that the apparatus is to exit the power-managed state, and wherein the apparatus is configured to alter the programmable setting in response to the indication.

12. The apparatus of claim 9, wherein the power management unit is configured to alter the programmable setting in response to an indication specifying that the first device is permitted to awaken from the power-managed state.

13. The apparatus of claim 9, further comprising:

the power management unit, wherein the power management unit is configured to clock gate the first device in response to the apparatus entering a power-managed state, wherein the register is configured to be accessible by a driver of the power management unit, wherein the driver is executable to set the programmable setting.

14. The apparatus of claim 8, wherein the first device includes a processor configured to perform encryption and decryption operations.

15. An apparatus, comprising:

a power management unit configured to manage power in a circuit, wherein the power management unit includes a register programmable with an indication that controls whether the circuit awakens from a power-managed state in response to an attempted communication with the circuit.

16. The apparatus of claim 15, wherein the power management unit is configured to:

receive a first indication from a driver of the power management unit, wherein the first indication specifies that the circuit is preparing to enter the power-managed state; and

receive a second indication from the circuit, wherein the second indication specifies the circuit is prepared to enter the power-managed state.

17. The apparatus of claim 16, wherein the power management unit is configured to:

in response to receiving the second indication;

gate a clock signal for the circuit; and

store an indication in the register specifying that the circuit is not permitted to receive an attempted communication.

18. The apparatus of claim 17, wherein the power management unit is configured to provide the indication to a fabric facilitating the attempted communication with the circuit, wherein the fabric is configured to determine, based on the provided indication, whether to permit the attempted communication with the circuit.

19. The apparatus of claim 18, wherein the fabric is configured to reject the attempted communication in response to the power management unit indicating that the attempted communication is not permitted awaken the circuit.

20. The apparatus of claim 15, further comprising:

a processor configured to instruct the circuit to enter the power managed state; and

wherein the processor is configured to set a value of the register to restrict communications with the circuit.