MULTILAYER CERAMIC CAPACITOR AND MOUNTING BOARD HAVING MULTILAYER CERAMIC CAPACITOR MOUNTED THEREON

• US 20140209362A1
• Filed: 04/26/2013
• Published: 07/31/2014
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: PARK, Min Cheol, PARK, Sang Soo, AHN, Young Ghyu, LEE, Byoung Hwa
• Granted Patent: US 9,093,223 B2
• Time in Patent Office: Days
• US Class Current: 174/260
• CPC Class Codes: H01G 2/065 for surface mounting, e.g. chip capacitors
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/12 Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence

Abstract

A multilayer ceramic capacitor includes: a ceramic body having laminated dielectric layers having an average thickness of 0.2-2.0 μm; an active layer including first and second internal electrodes alternately exposed through end surfaces of the ceramic body having the dielectric layer interposed therebetween and contributing to capacitance formation; upper and lower cover layers respectively formed above and below the active layer, the lower cover layer being thicker than the upper cover layer; first and second external electrodes covering the end surfaces of the ceramic body, wherein a bottommost internal electrode adjacent to the lower cover layer has an oxide layer formed on at least one of top and bottom surfaces thereof, and when lengths and thicknesses of the bottommost internal electrode and the oxide layer are denoted by ‘L_e,’ ‘t_e’ and ‘L_o,’ ‘t_o’, respectively, in a cross section of the ceramic body taken in length-thickness direction, 50%<L_o/L_e×100 and 30%<t_o/t_e×100<80% are satisfied.

Claims

1. A multilayer ceramic capacitor, comprising:

a ceramic body having a plurality of dielectric layers laminated therein, the dielectric layers respectively having an average thickness of 0.2 to 2.0 μ

m;

an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body having the dielectric layer interposed therebetween and contributing to capacitance formation;

an upper cover layer formed above the active layer;

a lower cover layer formed below the active layer, the lower cover layer being thicker than the upper cover layer; and

first and second external electrodes covering the end surfaces of the ceramic body,

wherein a bottommost internal electrode adjacent to the lower cover layer has an oxide layer formed on at least one of top and bottom surfaces thereof, and

when a length and a thickness of the bottommost internal electrode are denoted by L_e and t_e, respectively, and a length and a thickness of the oxide layer are denoted by L_o and t_o, respectively, in a cross section of the ceramic body taken in length and thickness directions, 50%<

L_o/L_e×

100 and 30%<

t_o/t_e×

100<

80% are satisfied.

2. The multilayer ceramic capacitor of claim 1, wherein when A denotes half of an overall thickness of the ceramic body, B denotes a thickness of the lower cover layer, C denotes half of an overall thickness of the active layer, and D denotes a thickness of the upper cover layer, a ratio of deviation of a center portion of the active layer from a center portion of the ceramic body, (B+C)/A, satisfies 1.063≦

(B+C)/A≦

1.745.

3. The multilayer ceramic capacitor of claim 1, wherein when B denotes a thickness of the lower cover layer and D denotes a thickness of the upper cover layer, a ratio of the thickness of the upper cover layer to the thickness of the lower cover layer, D/B, satisfies 0.021≦

D/B≦

0.422.

4. The multilayer ceramic capacitor of claim 1, wherein when A denotes half of an overall thickness of the ceramic body and B denotes a thickness of the lower cover layer, a ratio of the thickness of the lower cover layer to half of the overall thickness of the ceramic body, B/A, satisfies 0.329≦

B/A≦

1.522.

5. The multilayer ceramic capacitor of claim 1, wherein when B denotes a thickness of the lower cover layer and C denotes half of an overall thickness of the active layer, a ratio of half of the overall thickness of the active layer to the thickness of the lower cover layer, C/B, satisfies 0.146≦

C/B≦

2.458.

6. The multilayer ceramic capacitor of claim 1, wherein a point of inflection formed on each of both end surfaces of the ceramic body is positioned at a height equal to or below a center of the ceramic body, due to a difference between a deformation rate occurring in a center portion of the active layer and a deformation rate occurring in the lower cover layer, at the time of application of voltage.

7. The multilayer ceramic capacitor of claim 1, wherein the dielectric layers are laminated in an amount of 150 layers or more.

8. A mounting board having a multilayer ceramic capacitor mounted thereon, the mounting board comprising:

a printed circuit board having first and second electrode pads formed thereon; and

a multilayer ceramic capacitor mounted on the printed circuit board,

wherein the multilayer ceramic capacitor includes;

a ceramic body having a plurality of dielectric layers laminated therein, the dielectric layers respectively having an average thickness of 0.2 to 2.0 μ

m;

an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body having the dielectric layer interposed therebetween and contributing to capacitance formation;

an upper cover layer formed above the active layer;

a lower cover layer formed below the active layer, the lower cover layer being thicker than the upper cover layer; and

first and second external electrodes covering both end surfaces of the ceramic body while being connected to the first and second electrode pads through soldering, and

wherein a bottommost internal electrode adjacent to the lower cover layer has an oxide layer formed on at least top and bottom surfaces thereof, and

when a length and a thickness of the bottommost internal electrode are denoted by L_e and t_e, respectively, and a length and a thickness of the oxide layer are denoted by L_o and t_o, respectively, in a cross section of the ceramic body taken in length and thickness directions, 50%<

L_o/L_e×

100 and 30%<

t_o/t_e×

100<

80% are satisfied.

9. The mounting board of claim 8, wherein when A denotes half of an overall thickness of the ceramic body, B denotes a thickness of the lower cover layer, C denotes half of an overall thickness of the active layer, and D denotes a thickness of the upper cover layer, a ratio of deviation of a center portion of the active layer from a center portion of the ceramic body, (B+C)/A, satisfies 1.063≦

(B+C)/A≦

1.745.

10. The mounting board of claim 8, wherein when B denotes a thickness of the lower cover layer and D denotes a thickness of the upper cover layer, a ratio of the thickness of the upper cover layer to the thickness of the lower cover layer, D/B, satisfies 0.021≦

D/B≦

0.422.

11. The mounting board of claim 8, wherein when A denotes half of an overall thickness of the ceramic body and B denotes a thickness of the lower cover layer, a ratio of the thickness of the lower cover layer to half of the overall thickness of the ceramic body, B/A, satisfies 0.329≦

B/A≦

1.522.

12. The mounting board of claim 8, wherein when B denotes a thickness of the lower cover layer and C denotes half of an overall thickness of the active layer, a ratio of half of the overall thickness of the active layer to the thickness of the lower cover layer, C/B, satisfies 0.146≦

C/B≦

2.458.

13. The mounting board of claim 8, wherein a point of inflection formed on each of both end surfaces of the ceramic body is positioned at a height equal to or below the soldering, due to a difference between a deformation rate occurring in a center portion of the active layer and a deformation rate occurring in the lower cover layer, at the time of application of voltage.

14. The mounting board of claim 8, wherein the dielectric layers are laminated in an amount of 150 layers or more.