PIXEL UNIT AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

• US 20140209912A1
• Filed: 01/22/2014
• Published: 07/31/2014
• Est. Priority Date: 01/25/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Zheng, Soon, Im Jang
• Granted Patent: US 9,431,434 B2
• Time in Patent Office: Days
• US Class Current: 257/71
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are performed on a polysilicon layer so as to form heavily doped regions of a thin film transistor and a lower electrode of a storage capacitor respectively, thereby reducing numbers of photolithography and masking processes required to manufacture a LTPS-TFT, shortening time periods for development and mass production, and reducing complexity of processes as well as monitoring difficulty, and decreasing the production cost. The present invention further provides a pixel unit manufactured according to the method, an array substrate and a display device including the same.

Claims

1. A method of manufacturing a pixel unit, including steps of:

forming a polysilicon layer on a substrate;

performing a single patterning process on the polysilicon layer so as to form an active region of a thin film transistor and a lower electrode region of a storage capacitor; and

performing a single doping process on the active region and the lower electrode region so as to form heavily doped regions of the thin film transistor and a lower electrode of the storage capacitor respectively.

2. The method of manufacturing a pixel unit according to claim 1, wherein, before the doping process, the method further includes step of:

forming a first insulating layer on the polysilicon layer, portions of the first insulating layer being used as a gate insulating layer of the thin film transistor and a dielectric layer of the storage capacitor.

3. The method of manufacturing a pixel unit according to claim 2, wherein, after the doping process, the method further includes steps of:

forming a gate of the thin film transistor and an upper electrode of the storage capacitor on the first insulating layer;

forming a second insulating layer on the first insulating layer, the gate and the upper electrode; and

processing the substrate so that an ion activation reaction and a hydrogenation reaction occur in the active region and the lower electrode region.

4. The method of manufacturing a pixel unit according to claim 3, wherein, after the ion activation reaction and the hydrogenation reaction have occurred in the active region and the lower electrode region, the method further includes steps of:

forming a planarization layer on the second insulating layer;

forming through holes within the planarization layer, the second insulating layer and the gate insulating layer; and

forming pixel electrodes on the planarization layer to cover the through holes.

5. The method of manufacturing a pixel unit according to claim 4, further including step of:

forming a pixel definition layer to cover the pixel electrodes and the second insulating layer, wherein in the pixel definition layer is formed therein with an opening for accommodating a light emitting material.

6. The method of manufacturing a pixel unit according to claim 1, wherein the heavily doped regions include a source region and a drain region of the thin film transistor.

7. The method of manufacturing a pixel unit according to claim 6, further including step of:

forming lightly doped regions on inner sides of the heavily doped regions.

8. The method of manufacturing a pixel unit according to claim 1, wherein, the step of forming the polysilicon layer includes:

forming a amorphous silicon film on the substrate; and

converting the amorphous silicon film into the polysilicon layer.

9. The method of manufacturing a pixel unit according to claim 8, wherein, the step of converting the amorphous silicon film into the polysilicon layer includes:

converting the amorphous silicon film into the polysilicon layer through one or more of an excimer laser crystallization process, a metal induced crystallization process, and a solid phase crystallization process.

10. The method of manufacturing a pixel unit according to claim 2, wherein, before forming the polysilicon layer, the method further includes:

forming a buffer layer on the substrate.

11. A pixel unit, including:

a substrate; and

a thin film transistor and a storage capacitor formed on the substrate, wherein heavily doped regions of the thin film transistor and a lower electrode of the storage capacitor are made of the same materials and are formed simultaneously through a single patterning process and a single doping process.

12. The pixel unit according to claim 11, wherein the heavily doped regions and the lower electrode are formed in the same polysilicon layer.

13. The pixel unit according to claim 12, further including a first insulating layer formed on the polysilicon layer, wherein portions of the first insulating layer are used as a gate insulating layer of the thin film transistor and a dielectric layer of the storage capacitor.

14. The pixel unit according to claim 13, further including:

a gate of the thin film transistor and an upper electrode of the thin film transistor, which are formed on the first insulating layer; and

a second insulating layer formed on the gate and the upper electrode.

15. The pixel unit according to claim 14, further including:

a planarization layer formed on the second insulating layer;

through holes formed within the planarization layer, the second insulating layer and the gate insulating layer; and

pixel electrodes formed on the planarization layer to cover the through holes.

16. The pixel unit according to claim 15, further including:

a pixel definition layer covering the pixel electrodes and the second insulating layer, wherein the pixel definition layer is formed therein with an opening for accommodating a light emitting material.

17. The pixel unit according to claim 11, wherein the heavily doped regions include a source region and a drain region of the thin film transistor.

18. The pixel unit according to claim 12, further including a buffer layer formed between the substrate and the polysilicon layer.

19. An array substrate, including a plurality of pixel units as defined in claim 11.

20. A display device, including the array substrate as defined in claim 19.