Semiconductor Devices and Methods of Producing These

• US 20140210054A1
• Filed: 01/30/2013
• Published: 07/31/2014
• Est. Priority Date: 01/30/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kosub, Johann, Ledutke, Michael
• Granted Patent: US 9,202,753 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.

Claims

1. A method, comprising:

gluing with a releasable glue a reinforcing wafer to a semiconductor wafer thereby forming a composite wafer; and

dividing the composite wafer thereby generating a plurality of composite chips, each composite chip comprising a semiconductor chip and a reinforcing chip.

3. The method of claim 1, wherein the semiconductor wafer has a thickness less than 40 μ

m.

4. The method of claim 1, wherein applying the reinforcing wafer to the semiconductor wafer comprises applying the reinforcing wafer to a front side of the semiconductor wafer.

5. The method of claim 1, wherein applying the reinforcing wafer to the semiconductor wafer comprises applying the reinforcing wafer to a back side of the semiconductor wafer.

6. The method of claim 1, further comprising thinning the semiconductor wafer before applying the reinforcing wafer to the semiconductor wafer.

7. The method of claim 1, further comprising thinning the semiconductor wafer after applying the reinforcing wafer to the semiconductor wafer.

8. The method of claim 1, wherein the reinforcing wafer comprises a material selected from the group of consisting of glass, a resin material, copper, a copper alloy, a mold material and amorphous silicon.

9. The method of claim 1, further comprising attaching the plurality of composite chips to a temporary carrier.

10. The method of claim 9, further comprising applying an encapsulation material to the plurality of composite chips and the temporary carrier thereby generating an artificial wafer.

11. The method of claim 10, further comprising releasing the artificial wafer from the temporary carrier.

12. The method of claim 1, further comprising bonding at least one of the plurality of composite chips to a substrate.

13. The method of claim 12, wherein the at least one of the plurality of composite chips is bonded to the substrate with the semiconductor chip facing the substrate.

14. The method of claim 12, further comprising:

releasably attaching the plurality of composite chips to an attach panel; and

bonding the plurality of composite chips to the substrate in a batch process.

15. The method of claim 12, further comprising separating the reinforcing chip from the semiconductor chip during or after bonding the at least one of the plurality of composite chip.

16. The method of claim 15, wherein bonding the at least one of the plurality of composite chips to the substrate and separating the reinforcing chip from the semiconductor chip is performed within a single thermal process.

17. The method of claim 12, further comprising depositing a metal onto the substrate to embed the semiconductor chip in the deposited metal.

18. The method of claim 17, wherein a main surface of the at least one of the semiconductor chips facing away from the substrate and an outer surface of the deposited metal are at the same level with each other within a tolerance of less than 2 μ

m.

2. (canceled)

19-25. -25. (canceled)

26. A method, comprising:

applying a reinforcing wafer to a semiconductor wafer thereby forming a composite wafer;

dividing the composite wafer thereby generating a plurality of composite chips, each composite chip comprising a semiconductor chip and a reinforcing chip;

bonding at least one of the plurality of composite chips to a substrate; and

separating the reinforcing chip from the semiconductor chip during or after bonding the at least one of the plurality of composite chip.

27. The method of claim 26, wherein bonding the at least one of the plurality of composite chips to the substrate and separating the reinforcing chip from the semiconductor chip is performed within a single thermal process.

28. The method of claim 26, wherein the semiconductor wafer has a thickness less than 40 μ

m.

29. The method of claim 28, wherein the reinforcing wafer comprises a material selected from the group of consisting of glass, a resin material, copper, a copper alloy, a mold material and amorphous silicon.

30. A method, comprising:

applying a reinforcing wafer to a semiconductor wafer thereby forming a composite wafer;

thinning the semiconductor wafer after applying the reinforcing wafer to the semiconductor wafer; and

dividing the composite wafer thereby generating a plurality of composite chips, each composite chip comprising a semiconductor chip and a reinforcing chip.

31. The method of claim 30, wherein the semiconductor wafer has a thickness less than 40 μ

m.

32. The method of claim 30, wherein the reinforcing wafer comprises a material selected from the group of consisting of glass, a resin material, copper, a copper alloy, a mold material and amorphous silicon.