METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME

• US 20140210055A1
• Filed: 03/28/2014
• Published: 07/31/2014
• Est. Priority Date: 07/06/2011
• Status: Abandoned Application

• Current Assignee: Gil-Heyun Choi, Hei-Seung Kim, In-Sun Park, Ji-Soon Park, Jong-Myeong Lee, Jong-Won Hong
• Original Assignee: Gil-Heyun Choi, Hei-Seung Kim, In-Sun Park, Ji-Soon Park, Jong-Myeong Lee, Jong-Won Hong
• Inventors: PARK, In-sun, CHOI, Gil-heyun, PARK, Ji-soon, LEE, Jong-myeong, HONG, Jong-won, KIM, Hei-seung
• Application Number:
  US14/228,820
• Publication Number:
  US 20140210055A1
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Claims

1-53. -53. (canceled)

54. A semiconductor device comprising:

a semiconductor substrate including a dummy region adjacent to an active line region,

the active line region including cell trenches,

the dummy region including dummy trenches;

a plurality of cell lines in the cell trenches,

the plurality of cell lines separated by first width; and

a plurality of dummy lines in the dummy trenches,

the plurality dummy lines separated by a second width that is greater than the first width.

55. The semiconductor device of claim 54, wherein

the plurality of dummy lines includes at least two dummy lines connected to each other at ends of the at least two dummy lines.

56. The semiconductor device of claim 55, wherein a ratio of a width to a distance of the plurality of dummy lines is about 1:

2.5 and about 1;

3.

57. The semiconductor device of claim 54, wherein

the plurality of dummy lines have wider widths at ends of the dummy lines than widths at other parts of the dummy lines.

58. The semiconductor device of claim 54, wherein at least one of the cell lines and the dummy lines include one of Cu and a Cu alloy.

59. A semiconductor memory device comprising:

a string selection line (SSL) and a ground selection line (GSL) on a substrate;

a group of wordlines extending in a first direction between the string selection line (SSL) and the ground selection line (GSL);

a first bitline set and a second bit line set on the group of wordlines,

the first bitline set and the second bitline set extending in a second direction,

the second direction being different from the first direction, and

the first bitline set and the second bitline set are electrically connected to the SSL;

a common source line (CSL) that is electrically connected to the GSL; and

a plurality of dummy bitlines between the first and second bitline sets,

the plurality of dummy bitlines having a level that is equal to a level of the first and second bitline sets, and

the dummy bitlines separated by a first distance that is greater than a second distance separating at least two bitlines of the first bitline set.

60. The semiconductor memory device of claim 59, further comprising:

CSL taps electrically connected to the CSL,

wherein a level of the CSL taps is equal to the level of the dummy bitlines.

61. The semiconductor memory device of claim 59, wherein

the level of the common source line (CSL) is higher than a level of the wordlines, and

the level of the common source line (CSL) is lower than the levels of the first and second bitline sets.

62. The semiconductor memory device of claim 59, wherein the dummy bitlines are physically connected to the SSL through vias.

63. The semiconductor memory device of claim 59, wherein at least two of the dummy bitlines are connected to each other.

64-67. -67. (canceled)