INTEGRATED CIRCUIT PACKAGE WITH ACTIVE INTERPOSER

• US 20140210097A1
• Filed: 01/29/2013
• Published: 07/31/2014
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chen, Shuxian, Watt, Jeffrey T.
• Granted Patent: US 9,633,872 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Claims

1. An integrated circuit package comprising:

a substrate;

an interposer having a plurality of embedded switching elements disposed over the substrate, wherein the plurality of embedded switching elements are operable to receive a plurality of power supply signals; and

an integrated circuit having a plurality of circuit blocks disposed over the substrate, wherein the plurality of embedded switching elements is operable to provide at least one circuit block of the plurality of circuit blocks with a selected power supply signal of the plurality of power supply signals.

2. The integrated circuit package defined in claim 1, wherein each circuit block of the plurality of circuit blocks includes a control circuit operable to control at least one embedded switching element from the plurality of embedded switching elements.

3. The integrated circuit package defined in claim 2, wherein the plurality of embedded switching elements comprises a plurality of transistors each having a source-drain terminal coupled to receive a power supply signal of the plurality of power supply signals, and wherein each control circuit is operable to control a respective set of embedded switching elements of the plurality of embedded switching elements.

4. The integrated circuit package defined in claim 3, wherein the control circuit is operable to provide a control signal to a gate of at least one transistor of the plurality of transistors and wherein the control circuit is operable to activate the transistor using the control signal.

5. The integrated circuit package defined in claim 3 wherein the plurality of transistors comprises a plurality of P-type metal-oxide-field-effect-transistors.

6. The integrated circuit package defined in claim 1, wherein the interposer comprises a substrate layer and a plurality of redistribution layers, wherein the plurality of redistribution layers comprises a plurality of interconnects that is coupled to the integrated circuit, wherein the plurality of embedded switching elements is formed in the substrate layer, and wherein the plurality of embedded switching elements is coupled to the integrated circuit through the plurality of interconnects.

7. The integrated circuit package defined in claim 1 further comprising:

an additional integrated circuit disposed over the interposer, wherein the plurality of switching elements in the interposer is operable to transmit a plurality of power supply signals to the integrated circuit and the additional integrated circuit.

8. An integrated circuit device comprising:

an integrated circuit having a plurality of logic regions, wherein a first portion of the plurality of logic regions is operable to receive a first power supply signal and wherein a second portion of the plurality of logic regions is operable to receive a second power supply signal; and

an interposer having a plurality of switching elements coupled to the integrated circuit, wherein a first switching element is operable to provide the first portion of the plurality of logic regions with the first power supply signal, and wherein a second switching element is operable to provide the second portion of the plurality of logic regions with the second power supply signal.

9. The integrated circuit device defined in claim 8, wherein the first and second power supply signals comprise first and second voltage levels, respectively, wherein the first switching element is further operable to provide the second portion of the plurality of logic regions with the first power supply signal and wherein the second switching element is further operable to provide the first portion of the plurality of logic regions with the second power supply signal.

10. The integrated circuit device defined in claim 8, wherein each switching element of the plurality of switching elements is selected from the group consisting of:

a P-type metal-oxide-field-effect-transistor, an N-type metal-oxide-field-effect-transistor, and a Micro-Electro-Mechanical switches.

11. The integrated circuit device defined in claim 8 further comprising:

first control circuitry in the first portion of the plurality of logic regions; and

second control circuitry in the second portion of the plurality of logic regions, wherein the first and second control circuitries are operable to selectively enable the first and second switching elements, respectively.

12. The integrated circuit device defined in claim 11, wherein the first and second control circuitries are operable to receive a control signal selected from the group consisting of:

a configuration random access memory bit, a user input, an output signal from external circuitry, and a predetermined voltage level.

13. The integrated circuit device defined in claim 8 further comprising:

an additional integrated circuit coupled to the interposer layer, wherein the additional integrated circuit comprises an additional plurality of logic regions, wherein the plurality of switching elements is operable to provide the additional plurality of logic regions with a plurality of power supply signals.

14. The integrated circuit device defined in claim 8, wherein the interposer comprises a substrate layer and a plurality of redistribution layers, wherein the plurality of redistribution layers includes a plurality of interconnects that is coupled to the integrated circuit, and wherein the plurality of switching elements is formed in the substrate layer.

15. The integrated circuit device defined in claim 14, wherein the substrate layer includes a plurality of through-silicon vias and wherein the plurality of switching elements is coupled to the integrated circuit through the plurality of interconnects in the plurality of redistribution layers.

16. A method of packaging an integrated circuit, the method comprising:

forming a plurality of switching elements in an interposer;

mounting the interposer on a package substrate; and

mounting an integrated circuit having a plurality of logic regions on the interposer, wherein each switching element of the plurality of switching elements is operable to provide the plurality of logic regions with a selected power supply signal through a plurality of interconnects.

17. The method defined in claim 16, wherein the interposer includes a substrate layer and a plurality of redistribution layers, and wherein forming the plurality of switching elements comprises:

depositing a silicon oxide layer over a dielectric layer on the substrate layer;

depositing a polysilicon layer over the silicon oxide layer;

removing a portion of the polysilicon layer and the silicon oxide layer to form at least one gate stack;

implanting a source region and a drain region in the substrate layer; and

forming a plurality of contacts over the source and drain regions and the at least one gate stack.

18. The method defined in claim 17 further comprising:

implanting an n-well region in the substrate, wherein implanting the source and drain regions in the substrate layer comprises implanting the source and drain regions in the n-well region.

19. The method defined in claim 16 further comprising:

mounting an additional integrated circuit having an additional plurality of logic regions on the interposer wherein each switching element of the plurality of switching elements is operable to provide the additional plurality of logic regions with an additional selected power supply signal through the plurality of interconnects.

20. The method defined in claim 16 further comprising:

forming a diode in the interposer prior to the disposing of the interposer over the package substrate.

21. The method defined in claim 16 further comprising:

forming a de-coupling capacitor in the interposer prior to the disposing of the interposer over the package substrate.