REDRIVER WITH OUTPUT RECEIVER DETECTION THAT MIRRORS DETECTED TERMINATION ON OUTPUT TO INPUT

• US 20140210509A1
• Filed: 11/14/2013
• Published: 07/31/2014
• Est. Priority Date: 10/23/2008
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Yeung, Tony, Zhang, Michael Y.
• Granted Patent: US 9,094,245 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H04B 3/36 Repeater circuits H04B3/58 takes precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834
• CPC Class Codes: H04L 25/029 Provision of high-impedance states
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Claims

1. A method for operating a repeater to mirror a termination impedance to an input comprising:

providing a connection to a first output termination resistance to an output of the repeater;

waiting for a measuring period of time to elapse after connecting the first output termination resistance to the output;

sensing the output to detect whether the termination impedance is connected; and

when connection of the termination impedance is detected, connecting an input termination resistance to an input of the repeater to mirror the termination impedance.

2. The method of claim 1 further comprising repeating detection of the termination impedance to re-detect the termination impedance after a re-detect period of time has elapsed, and switching the input termination resistance to the input to mirror the termination impedance.

3. The method of claim 1 further comprising repeating detection of the termination impedance to re-detect the termination impedance after each of a plurality of re-detect periods of time has elapsed.

4. The method of claim 1 further comprising:

sensing the input to detect an input signal; and

when the input signal is detected, connecting a second output termination resistance to the output and repeating the input signal to the output of the repeater for re-transmission.

5. The method of claim 1 wherein connecting the first output termination resistance to the output of the repeater occurs in response to a power-on signal or a reset signal.

6. A repeater device comprising:

a differential input including a true differential input and a complement differential input;

a differential output including a true differential output and a complement differential output;

a differential circuit, coupled to the differential input, for repeating data received to the differential output as re-transmitted data; and

an impedance mirror circuit, coupled to the differential output, for detecting a termination impedance on the differential output and for controlling an input termination on the differential input to reflect the termination impedance detected on the differential output, wherein the termination impedance is re-detected after a period of time has elapsed.

7. The repeater device of claim 6 further comprising a second impedance mirror circuit, coupled to the differential input, for detecting a signal on the differential input and for controlling an output termination on the true differential output.

8. The repeater device of claim 6 wherein the impedance mirror circuit comprises:

an output detector, coupled to the differential output, for sensing the termination impedance on the differential output and activating a detect signal in response to detection of the termination impedance; and

the input termination comprises,

a true switched input termination resistor, coupled to the true differential input in response to the detect signal being activated, and disconnected from the true differential input in response to the detect signal not being activated; and

a complement switched input termination resistor, coupled to the complement differential input in response to the detect signal being activated, and disconnected from the complement differential input in response to the detect signal not being activated.

9. The repeater device of claim 8 further comprising:

a first coupling capacitor coupled to the true differential input; and

a second coupling capacitor coupled to the complement differential input.

10. The repeater device of claim 6 wherein the repeater device is part of a communication chip.

11. The repeater device of claim 10 wherein the communication chip is compliant with the Peripheral Component Interconnect Express (PCIE) standard.

12. The repeater device of claim 6 wherein the differential circuit comprises:

an equalizer that shapes a waveform of the data received on the differential input to generate equalized data;

a pre-driver that receives the equalized data from the equalizer and generates buffered data; and

an output stage that receives the buffered data from the pre-driver and drives current onto the differential output.

19. The system of claim 6 wherein the differential circuit of the repeater comprises:

an equalizer that shapes a waveform of the data received on the differential input to generate equalized data;

a pre-driver that receives the equalized data from the equalizer and generates buffered data; and

an output stage that receives the buffered data from the pre-driver and drives current onto the differential output.

13. A system comprising:

a transmitter;

a receiver; and

a repeater comprising, a differential input coupled to the transmitter, a differential output coupled to the receiver, a differential circuit coupled between the differential input and the differential output and configured for repeating data received at the differential input from the transmitter at the differential output for transmission to the receiver as re-transmitted data, the repeater further comprising an impedance mirror circuit coupled to the differential output and configured for detecting a termination impedance on the differential output and for controlling an input termination on the differential input to reflect the termination impedance detected on the differential output, wherein the termination impedance is re-detected after a period of time has elapsed.

14. The system of claim 13 wherein the repeater further comprises a second impedance mirror circuit coupled to the differential input and configured for detecting a signal on the differential input and for controlling an output termination on the differential output.

15. The system of claim 13 wherein the differential input comprises a true differential input and a complement differential input, and the impedance mirror circuit of the repeater comprises:

an output detector, coupled to the differential output, for sensing the termination impedance on the differential output and activating a detect signal in response to detection of the termination impedance; and

the input termination comprises,

a true switched input termination resistor coupled to the true differential input in response to the detect signal being activated, and disconnected from the true differential input in response to the detect signal not being activated; and

a complement switched input termination resistor coupled to the complement differential input in response to the detect signal being activated, and disconnected from the complement differential input in response to the detect signal not being activated.

16. The system of claim 15 further comprising:

a first coupling capacitor coupled to the true differential input; and

a second coupling capacitor coupled to the complement differential input.

17. The system of claim 13 wherein the system is a communication chip.

18. The system of claim 13 wherein the communication chip is compliant with the Peripheral Component Interconnect Express (PCIE) standard.