Hierarchically Elaborated Phased-Array Antenna Modules and Method of Operation.

• US 20140210667A1
• Filed: 08/05/2013
• Published: 07/31/2014
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Tubis Technology Inc
• Original Assignee: Tubis Technology Inc
• Inventors: WANG, JAMES, CHIE, CHAK
• Granted Patent: US 10,439,284 B2
• Time in Patent Office: Days
• US Class Current: 342/372
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H01Q 3/2605 Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays
• CPC Class Codes: H01Q 3/2629 Combination of a main antenna unit with an auxiliary antenna unit
• CPC Class Codes: H01Q 3/34 by electrical means active lenses or reflecting arrays H01Q3/46

Abstract

A phased-array antenna panel mounts a plurality of front end modules to a Printed Circuit Board. Antenna elements, each controlled by a phased-array processing die, are individually configured to transform phase and gain according to a register array. The register array in each RFIC grouped into a local register group and a global register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a global register controlling overall RFIC function. The apparatus is configured to efficiently elaborate phase shift weights into a submodule of a phase array antenna system. Each subarray phase control submodule recursively elaborates weights to control phase shifters. Pairs of major operators and minor operators are received and transformed. Each submodule determines its own base phase shift weight per its unique configuration.

Claims

1. A submodule apparatus of an antenna array comprising:

a configuration store readable by a recursive adder;

a recursive adder coupled to the configuration store;

a plurality of phase shifter circuits coupled to the recursive adder and further each coupled to an external antenna array element;

an operand receiver coupled to the recursive adder and further communicatively coupled to a central control.

2. The apparatus of claim 1 wherein the configuration store further comprises

phase shift error correction bias for each element of the antenna array.

5. The submodule apparatus of claim 2 further comprising:

a configuration store;

a multiplier coupled to the configuration store;

a plurality of phase shifter circuits coupled to the multiplier and further each coupled to an external antenna array element;

an operand receiver coupled to the multiplier and further communicatively coupled to a central control.

6. The apparatus of claim 5 wherein the configuration store further comprises

phase shift error correction bias for each element of the antenna array.

11. The antenna array of claim 6 further comprising a phased-array antenna panel comprising:

a plurality of front end modules, Ball Grid Array(BGA)-mounted to a main PANEL Printed Circuit Board (PCB);

the main PANEL PCB;

each front end module comprising;

a plurality of antenna elements;

the antenna element coupled to a frontend die;

the frontend die coupled to a phased-array processing die;

wherein the antenna elements are embedded in the top of a substrate and the frontend dies and the phased-array processing die are flip-chip mounted onto the bottom layer of substrate of each front end module whereby input or output signals are conducted through the substrate to the phased-array processing die and to passive combiners and splitters embedded in the PANEL PCB; and

a transceiver die flip-chip mounted on the PANEL PCB whereby the antenna transmitted and received signals are frequency translated.

12. The Radio Frequency Integrated Circuit (RFIC) device of claim 11 further comprising:

a single bus coupling the following;

phased-array processing blocks;

phase-shifters, combiners, splitters, gain equalizers, buffer amplifiers, and

a digital signal control and interface circuit;

comprising

at least one global/individual indicator pad and

a plurality of individual die address setting pads enabling a first die address to be configured at a first location on the PCB which connects a plurality of die address pads to a first combination of logic high or logic low and a second die address to be configured at a second location on the PCB which connects a plurality of die address pads to a second combination of logic high or logic low whereby registers within the RFIC are assigned unique addresses and whereby indexing is provided for use in a computational mode.

13. The printed circuit board (PCB) of claim 12 further comprising a data and address bus a plurality of die address pads and a global die selection pad and a transfer format mode pad;

14. The PCB of claim 13 further comprising a driver to buffer the bus output;

the bus coupling a microcontroller master device and coupling a plurality of slave devices on each RFIC.

15. The RFIC of claim 14 further comprising a register array in each RFIC grouped into a local register group and a global register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a global register controlling overall RFIC function;

wherein at least one local register is a common register coupled to input output circuits of the RFIC and further coupled to other local registers to distribute data values for each of the antenna elements.

18. The RFIC of claim 15 comprising a single serial bus, the bus communicatively coupling a common register to a plurality of local registers, the bus further coupled to die address settings of the device whereby a single pointer is disseminated to all antenna elements or whereby an indexing can be determined in a computation mode of operation.

3. A method for operation of a phased-array antenna comprising at a submodule apparatus:

receiving a first major operand;

receiving a first and a second minor operand;

storing the first major operand as a base phase shift for the submodule;

recursively adding a first minor operand to the base phase shift to determine a first vector of phase shift weights for each of a plurality of shifters; and

recursively adding a second minor operand to each member of the first vector to determine phase shift weights for all the shifters.

4. The method of claim 3 further comprising

receiving a second major operand;

recursively adding the first and second major operands to determine a base phase shift for each submodule according to its configuration; and

adding the phase shift error correction bias for each element of the antenna array.

7. The method of claim 3 for operation of a submodule apparatus further comprising:

receiving a first major operand;

receiving a first and a second minor operand;

storing the first major operand as a base phase shift for the submodule;

multiplying a first minor operand with an index and adding to the base phase shift to determine a first vector of phase shift weights for each of a plurality of shifters; and

multiplying a second minor operand with an index and adding to each member of the first vector to determine phase shift weights for all the shifters.

8. The method of claim 7 further comprising

receiving a second major operand;

multiplying the first and second major operands with indexes to determine a base phase shift for each submodule according to its configuration; and

adding the phase shift error correction bias for each element of the antenna array.

9. The method for operation at a host processor communicatively coupled to a plurality of submodules of claim 8, the method further comprising:

determining a region that an antenna array of submodules will be pointing next R+1;

the host

determining that the region is adequately covered by one of a set of d phase weights previously associated with d directions for each element according to a content addressable memory store device wherein the phase weights are computed using an element index and a Submodule index; and

transmitting to each submodule an instruction to load a phase weight from the location d.

10. The method of operation of claim 9 for controlling slave RFIC devices in an antenna array further comprising:

initializing common registers with calibrated gain values;

storing phase shifter values in local registers;

computing phase shifter values; and

looking up gain settings.

16. The method of claim 10 further comprising a lookup method for determining antenna element phase and gain settings.

17. The method of claim 10 further comprising a computation method for determining antenna element phase and gain settings.

19. A method for transforming electrical signals by determining antenna weight vectors for a series of beam directions at digital functional logic circuits distributed among RFIC devices adjacent to their associated phased-array antenna element:

initializing local registers and common registers with integer-pair values for location of each antenna element in an phased-array antenna and a phase correction factor;

for each desired beam direction in the series of beam directions subsequent to initializing local registers and common registers,

reading four binary coded phase shift values from a serial bus;

storing the four binary coded phase shift values into common registers on each RFIC device accessible to each digital functional logic circuit associated with one of the phased-array antenna elements;

and at each digital functional logic circuit associated with one of the phased-array antenna elements,

reading from common registers a pair of binary coded phase shift increment values for each increment in module location on the printed circuit board and a pair of binary coded phase shift increment values for each increment in antenna element location on the module;

reading from common registers integer-pair values corresponding to the location of the module on a printed circuit board;

reading from common registers a phase correction factor;

reading from local registers associated with each digital functional logic circuit integer-pair values corresponding to the coordinate location of its associated phased-array antenna element in the phased-array antenna on a radiating surface of the module;

summing the phase correction factor and the multiplication products of the four binary coded phase shift values with their corresponding location-specific integer value;

setting an antenna phase shift and amplitude weight value for its phased-array antenna element according to a resolution; and

transforming the electrical signal according to the computed weight values.

20. The method of claim 19 wherein initializing local registers and common registers comprises:

writing m integer-pair values into common registers where m corresponds to a coordinate location of each module on a printed circuit board;

writing n integer-pair values into local registers where n corresponds to a coordinate location of an phased-array antenna element in the phased-array antenna on a radiating surface of the module; and

writing a binary coded value, within the range of 4 to 64 bits, for phase correction factor due to unequal trace lengths into local registers.