METAL OXIDE LAYER COMPOSITION CONTROL BY ATOMIC LAYER DEPOSITION FOR THIN FILM TRANSISTOR

• US 20140210835A1
• Filed: 01/25/2013
• Published: 07/31/2014
• Est. Priority Date: 01/25/2013
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Hong, John Hyunchul, Ryang, Hong-Son, Kim, Cheonhong, Fung, Tze-Ching
• Granted Patent: US 9,171,960 B2
• Time in Patent Office: Days
• US Class Current: 345/530
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD).

Claims

1. An thin film transistor (TFT) device, comprising:

a gate;

an active layer having a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the active layer includes at least two metal oxides, the at least two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the active layer;

a gate insulator between the active layer and the gate;

a source metal adjacent to the source region of the active layer; and

a drain metal adjacent to the drain region of the active layer.

2. The TFT device of claim 1, wherein the gate is over the gate insulator and the active layer is below the gate insulator.

3. The TFT device of claim 1, wherein the gate is below the gate insulator and the active layer is over the gate insulator.

4. The TFT device of claim 1, wherein the active layer substantially includes a substantially semiconducting metal oxide proximate the interface between the active layer and the gate insulator.

5. The TFT device of claim 1, wherein the active layer substantially includes a substantially insulating metal oxide proximate a surface of the active layer facing away from the gate.

6. The TFT device of claim 1, wherein the active layer includes indium-gallium-zinc-oxide (IGZO).

7. The TFT device of claim 6, wherein the concentration of gallium oxide increases from a surface of the active layer facing away from the gate to a surface of the active layer facing towards from the gate.

8. The TFT device of claim 7, wherein the concentration of gallium oxide is less than about 5% at the surface of the active layer facing away from the gate and greater than about 95% at the surface of the active layer facing towards the gate.

9. The TFT device of claim 1, wherein the active layer is less than about 100 Å

in thickness.

10. The TFT device of claim 1, wherein the active layer is amorphous.

11. The TFT device of claim 1, wherein one of the two metal oxides includes at least one of gallium oxide, aluminum oxide, hafnium oxide, and germanium oxide.

12. The TFT device of claim 1, wherein one of the two metal oxides includes at least one of indium oxide and zinc oxide.

13. The TFT device of claim 1, wherein the active layer is formed on a substrate, and wherein the substrate includes glass or plastic.

14. An apparatus comprising:

the TFT device of claim 1;

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

15. The apparatus of claim 14, further comprising:

a driver circuit configured to send at least one signal to the TFT device in electrical communication with the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

16. The apparatus of claim 14, further comprising:

an image source module configured to send the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter; and

an input device configured to receive input data and to communicate the input data to the processor.

17. A method comprising:

providing a substrate;

depositing by atomic layer deposition (ALD) a first metal oxide in a first deposition cycle;

depositing by ALD a second metal oxide in a second deposition cycle; and

forming a multi-component metal oxide semiconductor thin film on the substrate over a plurality of first deposition cycles and second deposition cycles in a deposition sequence, wherein the first deposition cycles occur with increasing frequency during the deposition sequence.

18. The method of claim 17, wherein depositing the first metal oxide includes:

pulsing a first metal precursor over the substrate; and

pulsing an oxidant precursor over the first metal precursor to form the first metal oxide.

19. The method of claim 18, wherein the first metal precursor includes one of an aluminum-containing precursor, a germanium-containing precursor, a hafnium-containing precursor, and a gallium-containing precursor.

20. The method of claim 18, wherein depositing the second metal oxide includes:

pulsing a second metal precursor over the substrate; and

pulsing an oxidant precursor over the second metal precursor to form the second metal oxide.

21. The method of claim 20, wherein the second metal precursor includes one of an indium-containing precursor and a zinc-containing precursor.

22. The method of claim 17, further comprising depositing by ALD a third metal oxide in a third deposition cycle, wherein forming the multi-component metal oxide semiconductor thin film on the substrate occurs over a plurality of first deposition cycles, second deposition cycles, and third deposition cycles in a deposition sequence.

23. The method of claim 17, wherein the substrate includes glass or plastic.

24. The method of claim 17, wherein providing the substrate includes pre-patterning the substrate with a hydrophobic photoresist, the hydrophobic photoresist having one or more openings to expose portions of the substrate such that the multi-component metal oxide semiconductor thin film is formed in the exposed portions of the substrate.

25. The method of claim 24, wherein depositing the first metal oxide or depositing the second metal oxide includes selectively depositing the first metal oxide or the second metal oxide on the exposed portions of the substrate.

26. The method of claim 24, further comprising selectively hydroxylating the exposed portion of the substrate.

27. The method of claim 24, wherein pre-patterning the substrate with the hydrophobic photoresist includes:

depositing hydrophobic photoresist over the substrate;

exposing a select portion of the hydrophobic photoresist to radiation through a photomask; and

etching the select portion of the hydrophobic photoresist to form the exposed portion of the substrate.

28. The method of claim 24, wherein the hydrophobic photoresist includes at least one of poly-methyl-methacrylate (PMMA), SU-8, and a fluorinated polymer.

29. The method of claim 17, further comprising:

pre-patterning the substrate with a hydrophobic photoresist, the hydrophobic photoresist having one or more openings to expose portions of the substrate such that the multi-component oxide semiconductor thin film is formed in the exposed portions of the substrate;

removing the hydrophobic photoresist to form a multi-component metal oxide semiconductor island on the substrate;

depositing a gate insulator over the multi-component metal oxide semiconductor island;

depositing a gate electrode over the gate insulator;

depositing a passivation insulator over the gate electrode;

patterning the passivation insulator and the gate insulator to selectively expose a source region of the multi-component metal oxide semiconductor island and a drain region of the multi-component metal oxide semiconductor island; and

depositing a source metal over the source region and a drain metal over the drain region.

30. The method of claim 17, further comprising:

providing a gate electrode below the substrate, wherein the substrate includes a dielectric material defining a gate insulator between the gate electrode and the multi-component metal oxide semiconductor thin film;

pre-patterning the substrate with a hydrophobic photoresist, the hydrophobic photoresist having one or more openings to expose portions of the substrate such that the multi-component oxide semiconductor thin film is formed in the exposed portions of the substrate;

removing the hydrophobic photoresist to form a multi-component metal oxide semiconductor island on the substrate;

depositing a source metal adjacent to a portion of the multi-component metal oxide semiconductor island; and

depositing a drain metal adjacent to another portion of the multi-component metal oxide semiconductor island.

31. The method of claim 17, wherein the first metal oxide and the second metal oxide each include at least one of aluminum, copper, zinc, gallium, germanium, arsenic, silver, cadmium, indium, tin, antimony, gold, mercury, titanium, lead, bismuth, and hafnium.

32. An apparatus, comprising:

a substrate; and

a thin film transistor (TFT) over the substrate, the TFT comprising;

a gate metal over the substrate;

a dielectric layer over the substrate and the gate metal;

an oxide semiconductor layer over the dielectric layer, wherein the oxide semiconductor layer has a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the oxide semiconductor layer includes at least two metal oxides, the at least two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer;

a source metal adjacent to the source region of the oxide semiconductor layer; and

a drain metal adjacent to the drain region of the oxide semiconductor layer.

33. The apparatus of claim 32, wherein the oxide semiconductor layer substantially includes a substantially semiconducting metal oxide proximate the lower surface of the oxide semiconductor layer.

34. The apparatus device of claim 32, wherein the oxide semiconductor layer includes indium-gallium-zinc-oxide (IGZO).

35. The apparatus of claim 32, wherein the oxide semiconductor layer is less than about 100 Å

in thickness.

36. An apparatus, comprising:

a substrate; and

a thin film transistor (TFT) over the substrate, the TFT comprising;

an oxide semiconductor layer over the substrate, wherein the oxide semiconductor layer has a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the oxide semiconductor layer includes at least two metal oxides, the at least two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer;

a dielectric layer over the channel region of the oxide semiconductor layer;

a gate metal over the dielectric layer;

a source metal adjacent to the source region of the oxide semiconductor layer; and

a drain metal adjacent to the drain region of the oxide semiconductor layer.

37. The apparatus of claim 36, wherein the oxide semiconductor layer substantially includes a substantially semiconducting metal oxide proximate the upper surface of the oxide semiconductor layer.

38. The apparatus device of claim 36, wherein the oxide semiconductor layer includes indium-gallium-zinc-oxide (IGZO).

39. The apparatus of claim 36, wherein the oxide semiconductor layer is less than about 100 Å

in thickness.