COOPERATIVE FLASH MEMORY CONTROL

• US 20140215129A1
• Filed: 02/14/2013
• Published: 07/31/2014
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, LLC
• Inventors: Kuzmin, Andrey V., Jadon, Mike, Mathews, Richard M.
• Granted Patent: US 9,652,376 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

Claims

1. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:

at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the memory array;

logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and

logic operable to send to a host information regarding at least one of the physical storage locations of the at least one memory array in dependence on the information retained in the management table.

2. The memory controller of claim 1, where the memory controller is embodied in a first integrated circuit, where the at least one interface is embodied as at least one first interface, and where the memory controller further comprises a second interface operable to exchange the data with at least one memory integrated circuit in association with the memory commands.

3. The memory controller of claim 1, where the memory is flash memory, where each physical storage location includes at least one page of flash memory and where the memory controller is embodied as a flash memory controller.

5. The memory controller of claim 3, where each physical storage location is exactly equal in size to an erase unit of NAND flash memory.

7. The memory controller of claim 1, where the information stored in the management table further includes metadata retained in the storage for each physical storage location, the metadata including a physical-to-logical mapping for data stored in the respective physical storage location.

8. The memory controller of claim 1, where the memory controller further comprises logic operable to receive a command that requests provision of information regarding at least one physical storage location of the memory array to a requesting host in dependence on the information stored in the management table, and where the logic operable to send the information to the host is operable to send the information regarding at least one physical storage location of the memory array to the requesting host in response to the command from the requesting host.

9. The memory controller of claim 8, where the logic operable to receive a command is operable to receive an asynchronous command, and where the memory controller is operable in response to the asynchronous command to establish at least one condition precedent prior to sending the requested information to the requesting host.

10. The memory controller of claim 9, where the logic operable to receive a command from the requesting host is further operable to receive a synchronous command from the requesting host, and where the memory controller is operable to send the requested information to the requesting host subject to at least one condition precedent in dependence on whether a command requesting the information regarding the at least one physical storage location of the memory array was a synchronous command type or an asynchronous command type.

11. The memory controller of claim 1, where the information stored in the management table for each physical storage location includes information indicating at least one of:

whether the respective physical storage location has been marked as bad;

number of erase operations performed on the respective physical storage location;

or

information representing page usage for all pages within the respective physical storage location.

12. The memory controller of claim 1, further comprising logic operable to interpret commands received from a requesting host via an interface of the at least one interface, where the commands received from the requesting host via the interface are compatible with a Nonvolatile Memory Express (NVMe) standard.

13. The memory controller of claim 1, where the logic operable to send the information to the host is operable to send the information in a manner that is not concurrently solicited.

14. The memory controller of claim 1, where the memory controller further comprises logic operable to perform for a given physical storage location a comparison with a threshold of at least one of (a) the information stored in the management table for the given physical storage location or (b) information derived from the information stored in the management table for the given physical storage location, and where the logic operable to send the information further comprises logic operable to generate an alert for a host responsive to the comparison.

15. The memory controller of claim 1, where the logic operable to send the information to the host is operable to send to the host information representing plural ones of the physical storage locations.

16. The memory controller of claim 15, where:

the information stored in the management table for each respective physical storage location includes information representing validity status of any data stored within the physical storage location;

the information representing validity status includes information identifying page utilization corresponding to the respective physical storage location; and

the information representing the plural ones of the physical storage locations is sufficient to identify candidate physical storage locations for space consolidation in dependence on whether, for each respective physical storage location, the information representing page utilization indicates that page utilization satisfies a threshold condition.

17. The memory controller of claim 16, where the information representing plural ones of the physical storage locations is sufficient to indicate an ordered list of at least two of the physical storage locations of the at least one memory array in order of increasing page utilization.

18. The memory controller of claim 1, where:

the information stored in the management table for each respective physical storage location includes information representing validity status of any data within the physical storage location;

the information representing validity status includes information identifying number of released pages corresponding to the respective physical storage location; and

the logic operable to send information to the host is operable to send information representing one or more unerased physical storage locations of the at least one memory array, including information dependent on relative number of released pages in each unerased physical storage location.

19. The memory controller of claim 1, where:

the information stored in the management table for each respective physical storage location includes information representing operability of memory cells within the physical storage location;

the information representing operability of memory cells includes information indicating whether the respective physical storage location has been marked as bad; and

the logic operable to send information to the host is operable to send information identifying one or more of the of the physical storage location of at least one memory array which have been marked as bad.

20. The memory controller of claim 1, where:

the information stored in the management table for each respective physical storage location includes information representing wear of the respective physical storage location; and

the logic operable to send information to the host is operable to send information identifying one or more physical storage locations of the at least one memory array for which the information representing wear indicates that the respective physical storage location is associated with wear satisfying a threshold condition.

21. The memory controller of claim 1, where:

the information stored in the management table for each respective physical storage location includes information representing a period since last data programming of valid data in the respective physical storage location; and

the logic operable to send information to the host is operable to send information identifying one or more physical storage locations of the at least one memory array for which the period represents satisfaction of a threshold condition.

32. The memory controller of claim 1, where the memory controller is embodied as an integrated circuit, and where the information for each physical storage location includes information indicating a cumulative erase count for the respective physical storage location.

33. The memory controller of claim 5, where the memory controller is to store information in the management table respective to each physical page of memory cells for each erase unit of the at least one memory array.

34. The memory controller of claim 5, where the information stored in the management table for each physical storage location includes page release information for the respective physical storage location.

35. The memory controller of claim 5, where the information stored in the management table for each physical storage location includes page release information for each page of plural pages in the respective physical storage location.

4. (canceled)

6. (canceled)

22. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:

means for receiving memory commands from a host and for exchanging data in association with the memory commands between a host and the memory array;

means for storing, in a management table accessible to the memory controller and for every physical storage location of the at least one memory array, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and

means for sending to a host information in dependence on the information retained by the memory controller.

23. An apparatus, comprising:

at least one flash memory array having physical storage locations; and

a flash memory controller having

at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the memory array,

logic operable to store, in a management table accessible to the flash memory controller and for every physical storage location of the at least one memory array, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid date within the physical storage location, or validity status of any data stored within the physical storage location, and

logic operable to send to a host information in dependence on the information.

24. The apparatus of claim 23, embodied as a system on-chip (SOC).

25. The apparatus of claim 23, embodied in a package multichip assembly where the flash memory controller comprises a first die and the at least one flash memory array comprises at least one second die.

26. The apparatus of claim 23, where the flash memory controller further comprises logic operable to receive from the host at least one of (a) a host command for identification of candidate memory units for a data relocation operation, or (b) a host command for identification of candidate erase units for an erase operation, and where the information to be sent to a host is responsive to the at least one of a host command for identification of candidate memory units or a host command for identification of candidate erase units.

27. The apparatus of claim 26, where the flash memory comprises NAND flash memory cells and where each physical storage location of the memory array comprises an integer number of one or more physical erase units or one or more physical pages.

28. The apparatus of claim 23, where the memory controller is externally programmable to define at least one threshold, where the memory controller further comprises logic operable to perform a comparison with the at least one threshold of at least one of (a) the information for a given physical storage location or (b) information derived from the information for a given physical storage location, and where the logic operable to send the information to the host further comprises logic operable to generate an alert for a host responsive to the comparison.

29. A memory controller integrated circuit, comprising:

at least one interface to receive memory commands from a host including commands to program pages of a NAND flash memory, to read physical pages of the NAND flash memory and to erase physical erase units of the NAND flash memory, where the NAND flash memory comprises physical storage locations that are each an integer number of at least one of (a) one or more physical pages of the NAND flash memory and (b) one or more physical erase units of the NAND flash memory;

logic operable to store, in a management table accessible to the memory controller integrated circuit and for at least each erase unit of the NAND flash memory, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid date within the physical storage location, of validity status of any data stored within the physical storage location; and

logic operable to service host queries for information dependent on the information, and to responsively transmit the information to a host.

30. The memory controller integrated circuit of claim 29, where the logic operable to service host queries is operable to receive at least one of (a) a host query for identification of at least one page of memory cells as a candidate for a data relocation operation, or (b) a host query for identification of at least one of the erase units as a candidate for an erase operation, and where the information is transmitted responsive to the at least one of a host query for identification of at least one page of memory cells as a candidate for a data relocation operation or a host query for identification of at least one of the erase units as a candidate for an erase operation.

36. The memory controller of claim 29, where the memory controller is to store information in the management table respective to each physical page of memory cells for each erase unit of the at least one memory array.

31. (canceled)

37. A memory controller to interact with a memory having at least one memory array, the memory controller comprising:

at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the memory array;

logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing page release status for each page of memory cells associated with the respective physical storage location; and

logic operable to send to a host information regarding at least one of the physical storage locations of the memory array in dependence on the page release status information retained in the management table.

38. The memory controller of claim 37, embodied as a flash memory controller, where each physical storage location is equal to at least one of a page of memory cells or an erase unit of memory cells.

39. the memory controller of claim 37, where the information stored in the management table for every physical storage location of the at least one memory array also indicates whether each page of memory cells associated with the respective physical storage location contains un-released, valid data, and where the logic is operable to send to the host information representing whether any one of the physical storage locations of the at least one memory array is a candidate for one of an erase operation or a valid data relocation operation.