AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS

• US 20140215415A1
• Filed: 01/31/2013
• Published: 07/31/2014
• Est. Priority Date: 01/31/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Dai, Vito, Capodieci, Luigi, WANG, Lynn
• Granted Patent: US 8,924,896 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Claims

1. A method comprising:

scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern;

determining a context of the difficult-to-manufacture pattern within the drawn semiconductor design layout based on determining neighboring features of the difficult-to-manufacture pattern;

determining, by a processor, a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern and based on the context by accounting for the neighboring features; and

replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

4. The method according to claim 1, further comprising determining an extraction radius for determining the neighboring features of the difficult-to-manufacture pattern, the extraction radius being based on a radius of influence of manufacturing effects.

5. The method according to claim 1, wherein the difficult-to-manufacture pattern comprises polygonal data or image data.

6. The method according to claim 1, further comprising:

determining the pre-determined correlation based on candidate corrected patterns that fix respective candidate difficult-to-manufacture patterns; and

storing the candidate corrected patterns with the respective candidate difficult-to-manufacture patterns as correlated corrected patterns and pre-characterized difficult-to-manufacture patterns.

7. The method according to claim 6, further comprising determining whether a candidate corrected pattern fixes a candidate difficult-to-manufacture pattern based on correction of an original violation of the candidate difficult-to-manufacture pattern and a determination of no design rule check faults and manufacturing faults generated by the candidate corrected pattern.

8. The method according to claim 7, wherein the design rule check faults are design rule check faults at a boundary of an extraction radius, the extraction radius being based on a radius of influence of manufacturing effects.

9. The method according to claim 1, comprising the difficult-to-manufacture pattern including at least one of a line-end extension hotspot, an active area-tuck hotspot, a cut-mask generation hotspot, a lithography hotspot, a double patterning technology issue, and an optical proximity correction optimization.

2. (canceled)

3. (canceled)

10. An apparatus comprising:

at least one processor; and

at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following;

scan a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern;

determine a context of the difficult-to-manufacture pattern within the drawn semiconductor design layout based on determining neighboring features of the difficult-to-manufacture pattern;

determine a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern and based on the context by accounting for the neighboring features; and

replace the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

13. An apparatus of claim 10, wherein the apparatus is further caused, at least in part, to determine an extraction radius for determining the neighboring features of the difficult-to-manufacture pattern, the extraction radius being based on a radius of influence of manufacturing effects.

14. An apparatus of claim 10, wherein the difficult-to-manufacture pattern comprises polygonal data or image data.

15. An apparatus of claim 10, wherein the apparatus is further caused, at least in part, to:

determine the pre-determined correlation based on candidate corrected patterns that fix respective candidate difficult-to-manufacture patterns; and

store the candidate corrected patterns with the respective candidate difficult-to-manufacture patterns as correlated corrected patterns and pre-characterized difficult-to-manufacture patterns.

16. An apparatus of claim 15, wherein the apparatus is further caused, at least in part, to determine whether a candidate corrected pattern fixes a candidate difficult-to-manufacture pattern based on correction of an original violation of the candidate difficult-to-manufacture pattern and a determination of no manufacturing faults and design rule check faults generated by the candidate corrected pattern.

17. An apparatus of claim 16, wherein the design rule check faults are design rule check faults at a boundary of an extraction radius, the extraction radius being based on manufacturing effects represented by the difficult-to-manufacture pattern.

18. An apparatus of claim 10, wherein the difficult-to-manufacture pattern includes at least one of a line-end extension hotspot, an active area-tuck hotspot, a cut-mask generation hotspot, a lithography hotspot, a double patterning technology issue, and an optical proximity correction optimization.

11. (canceled)

12. (canceled)

19. A method comprising:

scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout;

determining, by a processor, a match between the difficult-to-manufacture pattern and a pre-characterized difficult-to-manufacture pattern;

determining a context of the difficult-to-manufacture pattern within the drawn semiconductor design layout based on determining neighboring features of the difficult-to-manufacture pattern;

determining an extraction radius associated with the difficult-to-manufacture pattern based on the context by accounting for the neighboring features;

deleting a portion of the drawn semiconductor design layout based on the extraction radius and the difficult-to-manufacture pattern; and

replacing the deleted portion with a corrected portion based on the pre-characterized difficult-to-manufacture pattern.

20. The method according to claim 19, further comprising:

replacing the difficult-to-manufacture pattern within the deleted portion with a corrected pattern;

performing a check on the corrected pattern within the deleted portion to ensure a violation associated with the difficult-to-manufacture pattern is corrected; and

performing another check on the corrected pattern within the deleted portion to ensure no new design rule violations and manufacturing faults are generated.