METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER

• US 20140217480A1
• Filed: 02/01/2013
• Published: 08/07/2014
• Est. Priority Date: 02/01/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kronholz, Stephan, Patzer, Joachim
• Granted Patent: US 9,029,919 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

Claims

1. A method of forming a transistor, comprising:

forming a gate structure above a semiconducting substrate;

forming a plurality of recesses in said semiconducting substrate proximate said gate structure;

forming a semiconductor material that is at least partially positioned in said recesses;

forming at least one layer of silicon above said semiconductor material; and

forming a cap layer comprised of silicon/germanium on said at least one layer of silicon.

2. The method of claim 1, wherein said gate structure is a final gate structure for said transistor.

3. The method of claim 1, wherein, prior to forming said plurality of recesses in said semiconducting substrate, forming sidewall spacers adjacent a sidewall of said gate structure, and wherein forming said plurality of recesses comprises forming a plurality of recesses that are self-aligned relative to said sidewall spacers.

4. The method of claim 1, wherein forming said semiconductor material that is at least partially positioned in said recesses comprises performing at least one epitaxial deposition process to form said semiconductor material.

5. The method of claim 1, wherein forming said semiconductor material that is at least partially positioned in said recesses comprises forming a single layer of semiconductor material.

6. The method of claim 1, wherein forming said semiconductor material that is at least partially positioned in said recesses comprises forming a plurality of layers of at least one type of semiconductor material.

7. The method of claim 1, wherein forming said at least one layer of silicon comprises performing at least one epitaxial silicon deposition process to form said at least one layer of silicon.

8. The method of claim 1, wherein forming said cap layer comprised of silicon/germanium on said at least one layer of silicon comprises performing at least one epitaxial silicon deposition process to form said cap layer comprised of silicon/germanium.

9. The method of claim 1, wherein forming said cap layer comprised of silicon/germanium on said at least one layer of silicon comprises forming said cap layer comprised of silicon/germanium with a germanium concentration of at least 1%.

10. The method of claim 1, wherein said gate structure comprises a gate insulation layer and a gate electrode positioned above said gate insulation layer.

11. The method of claim 1, further comprising:

forming a layer of insulating material above said cap layer;

forming a contact opening in said layer of insulating material that exposes a portion of said cap layer;

performing at least one etching process through said opening in said layer of insulating material to remove said exposed portion of said cap layer and thereby expose portions of said at least one silicon layer;

forming a metal silicide region in said layer of silicon; and

forming a conductive contact in said contact opening, said conductive contact being conductively coupled to said metal silicide region and extending through said cap layer.

12. A method of forming a transistor, comprising:

forming a gate structure above a semiconducting substrate;

performing at least one etching process to form a plurality of recesses in said semiconducting substrate proximate said gate structure;

performing at least one epitaxial deposition process to form a semiconductor material that is at least partially positioned in said recesses;

performing at least one silicon epitaxial deposition process to form at least one layer of silicon on said semiconductor material; and

performing at least one epitaxial deposition process to form a cap layer comprised of silicon/germanium having a germanium concentration of up to 15% germanium.

13. The method of claim 12, further comprising, prior to performing said at least one etching process to form said plurality of recesses in said semiconductor substrate, forming sidewall spacers adjacent a sidewall of said gate structure, and wherein performing said at least one etching process to form said plurality of recesses comprises performing said at least one etching process to form said plurality of recesses that are self-aligned relative to said sidewall spacers.

14. The method of claim 12, wherein said semiconductor material that is at least partially positioned in said recesses is comprised of a single layer of semiconductor material.

15. The method of claim 12, wherein said semiconductor material that is at least partially positioned in said recesses is comprised of a plurality of layers of at least one type of semiconductor material.

16. The method of claim 12, further comprising:

forming a layer of insulating material above said cap layer;

forming a contact opening in said layer of insulating material that exposes a portion of said cap layer;

performing at least one etching process through said opening in said layer of insulating material to remove said exposed portion of said cap layer and thereby expose portions of said at least one silicon layer;

forming a metal silicide region in said layer of silicon; and

forming a conductive contact in said contact opening, said conductive contact being conductively coupled to said metal silicide region and extending through said cap layer.

17. A device, comprising:

a semiconducting substrate;

a gate structure positioned above said semiconducting substrate;

a plurality of recesses formed in said semiconducting substrate proximate said gate structure;

at least one layer of semiconductor material positioned at least partially in said recesses;

a layer of silicon positioned above said at least one layer of semiconductor material; and

a cap layer comprised of silicon/germanium positioned on said layer of silicon.

18. The device of claim 17, wherein said cap layer has a germanium concentration of up to 15% germanium.

19. The device of claim 17, wherein said semiconductor material is comprised of a single layer of semiconductor material.

20. The device of claim 17, wherein said semiconductor material is comprised of a plurality of layers of semiconductor material.

21. The device of claim 17, further comprising a conductive contact that extends through said cap layer and contacts a metal silicide region positioned above said semiconductor material.