A METHOD OF MAKING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE, AND A MEMORY CELL MADE THEREBY

• US 20140217489A1
• Filed: 08/08/2012
• Published: 08/07/2014
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Wang, Chunming, Qiao, Baowei, Zhang, Zufa, Zhang, Yi, Lu, Wen-Juei, Wang, Shiuh luen
• Granted Patent: US 9,190,532 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.

Claims

1. A non-volatile memory cell comprising:

a single crystalline substrate of a first conductivity type having a top surface;

a first region of a second conductivity type in said substrate along the top surface;

a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;

a channel region between the first region and the second region;

a word line gate positioned over a first portion of the channel region, immediately adjacent to the first region, said word line gate spaced apart from the channel region by a first insulating layer;

a floating gate positioned over another portion of the channel region, said floating gate having a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface;

said floating gate having a first side wall adjacent to but separated from the word line gate; and

a second side wall opposite the first side wall, wherein said second side wall and said upper surface forming a sharp edge, with said second side wall greater in length than said first side wall and said upper surface sloping upward from said first side wall to said second side wall;

a coupling gate positioned over the upper surface of the floating gate and insulated therefrom by a third insulating layer; and

an erase gate positioned adjacent to the second side wall of the floating gate;

said erase gate positioned over the second region and insulated therefrom.

2. The memory cell of claim 1 wherein said erase gate overhangs a portion of said floating gate.

3. A method of fabricating a non-volatile memory cell, said method comprising:

forming a first polysilicon layer on a first insulating layer on a single crystalline substrate;

forming a hard mask on the first polysilicon layer, with said had mask being positioned over a portion of the first polysilicon layer;

etching the first polysilicon layer so that the polysilicon slopes downward away from the hard mask;

forming a second insulating layer on said first polysilicon layer;

forming a second polysilicon layer on said second insulating layer;

masking and cutting said second polysilicon layer, said second insulating layer, and said first polysilicon layer;

removing the hard mask;

etching the first polysilicon layer in a region where the hard mask was removed;

forming a tunneling layer over the first polysilicon layer in the region where the first polysilicon layer was etched;

forming an erase gate in the region where the first polysilicon was etched and in portions adjacent to the locations where the second polysilicon layer, said second insulating layer, and said first polysilicon layer were cut; and

forming source and drain regions in said substrate.

4. The method of claim 3 wherein said hard mask is silicon nitride.

5. The method of claim 3 wherein said first insulating layer is silicon dioxide.

6. The method of claim 3 wherein said second insulating layer is a composite insulating layer of silicon dioxide, silicon nitride and silicon dioxide.

7. The method of claim 3 wherein said tunneling layer is silicon dioxide.

8. The method of claim 3 wherein said etching step forms a sharp edge in said first polysilicon layer between a surface of said first polysilicon layer immediately adjacent to said second insulating layer, and said first polysiclicon layer etched.

9. The method of claim 3, wherein said masking and cutting step further comprises:

forming a sacrificial layer;

anisotropically etching said sacrificial layer to form sacrificial spacer adjacent to said hard mask;

Using said sacrificial spacer to mask and cut.