HELICAL SPIRAL INDUCTOR BETWEEN STACKING DIE

• US 20140217546A1
• Filed: 02/06/2013
• Published: 08/07/2014
• Est. Priority Date: 02/06/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Kuo, Chin-Wei, Jeng, Min-Chie, Luo, Cheng-Wei
• Granted Patent: US 8,941,212 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0566 Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19042 : being an inductor

Abstract

The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

Claims

1. A multi-level integrated inductor, comprising:

a first inductive structure comprising a first conductive layer disposed onto a first integrated chip (IC) die;

a second inductive structure comprising a second conductive layer onto a second IC die vertically stacked onto the first IC die; and

a conductive interconnect structure located vertically between the first IC die and the second IC die and configured to electrically connect the first conductive layer to the second conductive layer.

2. The multi-level integrated inductor of claim 1, wherein the conductive interconnect structure comprises one or more micro-bumps or copper pillars.

3. The multi-level integrated inductor of claim 1, wherein the conductive interconnect structure comprises a ferrite compound.

4. The multi-level integrated inductor of claim 1, further comprising:

an underfill layer disposed between the first conductive layer and the second conductive layer and configured to enclose the conductive interconnect structure.

5. The multi-level integrated inductor of claim 1,

wherein the first inductive structure comprises a helical pattern that winds around a first axis, which is normal to the first IC die, for a first plurality of turns;

and

wherein the second inductive structure comprises a helical pattern that winds around a second axis, which is normal to the second IC die, for a second plurality of turns.

6. The multi-level integrated inductor of claim 5, wherein the first axis and the second axis are separated by a non-zero offset.

7. The multi-level integrated inductor of claim 1, further comprising:

a third inductive structure comprising a third conductive layer onto a third IC die vertically stacked onto the second IC die; and

a second conductive interconnect structure located vertically between the second IC die and the third IC die and configured to electrically connect the second conductive layer to the third conductive layer.

8. The multi-level integrated inductor of claim 1,

wherein the first inductive structure comprises a first serpentine pattern that winds along its length in a first direction and then in a second direction opposite the first direction;

and

wherein the second inductive structure comprises a second serpentine pattern that winds along its length in a first direction and then in a second direction opposite the first direction.

9. The multi-level integrated inductor of claim 1,

wherein the first conductive layer is disposed in a first pattern and the second conductive layer is disposed in a second pattern;

and

wherein the first pattern is a mirror image of the second pattern.

10. The multi-level integrated inductor of claim 1, wherein the conductive interconnect structure provides for a distance between the first inductive structure and the second inductive structure having a range of approximately 20 um to approximately 40 um.

11. The multi-level integrated inductor of claim 1,

wherein the first inductive structure comprises a first aluminum redistribution layer formed onto the first IC die;

and

wherein the second inductive structure comprises a second aluminum redistribution layer formed onto the second IC die.

12. A multi-level integrated inductor, comprising:

a first inductive structure comprising a first metal layer disposed in a first helical pattern on a first side of a first integrated chip (IC) die;

a second inductive structure comprising a second metal layer disposed in a second helical pattern on a first side of a second IC die, which faces a first side of the first IC die; and

a conductive interconnect structure located vertically between the first and second IC die and configured to electrically connect the first metal layer to the second metal layer.

13. The multi-level integrated inductor of claim 12, wherein the conductive interconnect structure comprises one or more micro-bumps or copper pillars.

14. The multi-level integrated inductor of claim 12, further comprising:

an underfill layer disposed between the first metal layer and the second metal layer and configured to enclose the conductive interconnect structure.

15. The multi-level integrated inductor of claim 12, wherein the conductive interconnect structure comprises a ferrite compound.

16. The multi-level integrated inductor of claim 12, wherein the conductive interconnect structure provides for a distance between the first inductive structure and the second inductive structure having a range of approximately 20 um to approximately 40 um.

17. A method of forming a multi-level integrated inductor, comprising:

forming a first inductive structure on a first side of a first integrated chip (IC) die;

forming second inductive structure on a first side of a second IC die; and

attaching the first side of the first IC die to the first side of the second IC die by way of a conductive interconnect structure that electrically connects the first inductive structure and the second inductive structure.

18. The method of claim 17,

wherein the first inductive structure comprises a helical pattern that winds around a first axis, which is normal to the first IC die, for a first plurality of turns;

and

wherein the second inductive structure comprises a helical pattern that winds around a second axis, which is normal to the second IC die, for a second plurality of turns.

19. The method of claim 17, wherein the conductive interconnect structure comprises one or more micro-bumps or copper pillars.

20. The method of claim 17, wherein the conductive interconnect structure comprises a ferrite compound.