CIRCUIT AND METHOD FOR FLICKER SUPPRESSION IN LIGHT EMITTING DIODES (LEDS)

• US 20140217911A1
• Filed: 02/02/2013
• Published: 08/07/2014
• Est. Priority Date: 02/02/2013
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Alexander Mednik
• Inventors: MEDNIK, ALEXANDER
• Granted Patent: US 8,907,580 B2
• Time in Patent Office: Days
• US Class Current: 315/209.R
• CPC Class Codes: H05B 45/375 using buck topology
• CPC Class Codes: H05B 45/382 with galvanic isolation between input and output
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A circuit for flicker suppression in a Light Emitting Diode (LED) has a latch. The latch has a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge. A trigger circuit is coupled to the latch. The trigger circuit sends a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D_max of a gate of a LED driver circuit.

Claims

1. A circuit for flicker suppression in a Light Emitting Diode (LED) comprising:

a latch, the latch having a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge; and

a trigger circuit coupled to the latch, the trigger circuit sending a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D_max of a gate of a LED driver circuit.

2. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1, wherein the trigger circuit has inputs coupled to a clock signal and the PWM pulse and an output coupled to the latch.

3. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1, wherein the trigger circuit comprises:

a plurality of logic gates; and

a delay circuit coupled to at last one of the plurality o logic gates.

4. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1, wherein the trigger circuit comprises:

a plurality of logic gates, wherein the plurality of logic gates provides the signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D_max of a gate of a LED driver circuit; and

a delay circuit coupled to at last one of the plurality o logic gates.

5. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 1, wherein the trigger circuit comprises:

a first logic gate having a first input coupled to a first output of the latch and a second input coupled to a PWM signal of the Led driver circuit;

a delay circuit coupled between the second input of the first logic gate and the PWM signal;

a second logic gate having a first input coupled to a second output of the latch and a second input coupled to the PWM signal of the Led driver circuit;

a third logic gate having a first input coupled to an output of the first logic gate and a second input coupled to an output of the second logic gate; and

a fourth logic gate having a first input coupled to an output of the third logic gate, a second input coupled to a clock signal; and

an output coupled to an input of the latch.

6. A circuit for flicker suppression in a Light Emitting Diode (LED) comprising:

means for removing a duty cycle limit D_max of a gate signal of an LED driver circuit past a decision point (DP) by terminating the gate signal upon meeting a reference signal sent to a comparator of the LED driver circuit.

7. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 6, wherein the means comprises:

a latch, the latch having a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge; and

a trigger circuit coupled to the latch, the trigger circuit sending a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D_max of a gate of a LED driver circuit.

8. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 7, wherein the trigger circuit has inputs coupled to a clock signal and the PWM pulse and an output coupled to the latch.

9. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 7, wherein the trigger circuit comprises:

a plurality of logic gates; and

a delay circuit coupled to at last one of the plurality o logic gates.

10. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 7, wherein the trigger circuit comprises:

a plurality of logic gates, wherein the plurality of logic gates provides the signal to the latch to change to the second state when a decision point occurs during a time following a duty limit D_max of a gate of a LED driver circuit; and

a delay circuit coupled to at last one of the plurality o logic gates.

11. The circuit for flicker suppression in a Light Emitting Diode (LED) in accordance with claim 7, wherein the trigger circuit comprises:

a first logic gate having a first input coupled to a first output of the latch and a second input coupled to a PWM signal of the Led driver circuit;

a delay circuit coupled between the second input of the first logic gate and the PWM signal;

a second logic gate having a first input coupled to a second output of the latch and a second input coupled to the PWM signal of the Led driver circuit;

a third logic gate having a first input coupled to an output of the first logic gate and a second input coupled to an output of the second logic gate; and

a fourth logic gate having a first input coupled to an output of the third logic gate, a second input coupled to a clock signal; and

an output coupled to an input of the latch.