MULTI-SUPPLY SEQUENTIAL LOGIC UNIT
First Claim
1. An apparatus comprising:
- a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and
a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal.
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Accused Products
Abstract
Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
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Citations
35 Claims
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1. An apparatus comprising:
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a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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providing an input signal to a data path including logic gates operating on a first power supply level; generating an output signal from the data path; providing a clock signal to a clock path including logic gates operating on a second power supply level; and generating a sampling signal by the logic gates of the clock path to sample the input signal for generating the output signal, wherein the second power supply level is higher than the first power supply level. - View Dependent Claims (15)
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16-21. -21. (canceled)
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22. A system comprising:
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a wireless connectivity; and a processor communicatively coupled to the wireless connectivity, the processor including; a sequential logic unit comprising; a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sample signal to generate the output signal. - View Dependent Claims (23, 25, 26, 27, 29, 31, 32, 34, 35)
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24. (canceled)
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28. (canceled)
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30. (canceled)
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33. (canceled)
Specification