APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS

• US 20140223226A1
• Filed: 12/22/2011
• Published: 08/07/2014
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Hisham Shafi
• Inventors: Yigzaw, Theodros, Srinivasa, Ganapati N., Vargas, Jose A., Mishaeli, Michael, Cohen, Ehud, Sperber, Zeev, Kumar, Mohan J., Santhanakrushnan, Geeyarpuram N., Shafi, Hisham, Raikin, Shlomo, Mandelblat, Julius Y.
• Granted Patent: US 10,223,204 B2
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1405 at machine instruction level

Abstract

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Claims

1. A method for detecting and recovering from data fetch errors within a processor core comprising:

detecting an error associated with data in response to a data fetch operation; and

responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

2. The method as in claim 1 wherein responsively performing one or more operations comprises attaching a poison indication to the data.

3. The method as in claim 2 further comprising:

transmitting the poison indication with the data down the processor pipeline to provide the poison indication to stages and units within the processor pipeline.

4. The method as in claim 3 wherein the poison indication is transmitted to a retirement unit to ensure that the retirement unit does not retire the data fetch operation which resulted in the error.

5. The method as in claim 1 wherein the error is detected in a chunk of data equal to a specified fraction of a cache line.

6. The method as in claim 5 wherein the chunk of data comprises one half of a cache line.

7. The method as in claim 6 wherein the cache line is 64 Bytes and the chunk of data comprises 32 Bytes.

8. The method as in claim 1 wherein detecting an error comprises executing an error correction code (ECC) operation on the data.

9. A data processing apparatus for detecting and recovering from data fetch errors comprising:

at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and

error processing logic in communication with the processing stages to perform the operations of;

detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and

responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

10. The apparatus as in claim 9 wherein responsively performing one or more operations comprises attaching a poison indication to the data.

11. The apparatus as in claim 10 wherein the error processing logic performs the additional operation of:

transmitting the poison indication with the data down the processor pipeline to provide the poison indication to stages and units within the processor pipeline.

12. The apparatus as in claim 11 wherein the poison indication is transmitted to a retirement unit to ensure that the retirement unit does not retire the data fetch operation which resulted in the error.

13. The apparatus as in claim 9 wherein the error is detected in a chunk of data equal to a specified fraction of a cache line.

14. The apparatus as in claim 13 wherein the chunk of data comprises one half of a cache line.

15. The apparatus as in claim 14 wherein the cache line is 64 Bytes and the chunk of data comprises 32 Bytes.

16. The apparatus as in claim 9 wherein detecting an error comprises executing an error correction code (ECC) operation on the data.

23. The computer system as in claim 13 wherein the cache line is 64 Bytes and the chunk of data comprises 32 Bytes.

17. A computer system comprising:

a central processing unit including at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage;

error processing logic in communication with the processing stages to perform the operations of;

detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and

responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage; and

at lease one input/output interface communicatively coupling the central processing unit to one or more input/output devices.

18. The computer system as in claim 17 wherein responsively performing one or more operations comprises attaching a poison indication to the data.

19. The computer system as in claim 18 wherein the error processing logic performs the additional operation of:

transmitting the poison indication with the data down the processor pipeline to provide the poison indication to stages and units within the processor pipeline.

20. The computer system as in claim 19 wherein the poison indication is transmitted to a retirement unit to ensure that the retirement unit does not retire the data fetch operation which resulted in the error.

21. The computer system as in claim 17 wherein the error is detected in a chunk of data equal to a specified fraction of a cache line.

22. The computer system as in claim 20 wherein the chunk of data comprises one half of a cache line.

24. The computer system as in claim 17 wherein detecting an error comprises executing an error correction code (ECC) operation on the data.