Domain-specific Hardwired Symbolic Machine

• US 20140223561A1
• Filed: 03/13/2013
• Published: 08/07/2014
• Est. Priority Date: 02/05/2013
• Status: Active Grant

• Current Assignee: Hackproof Technologies, Inc.
• Original Assignee: Hackproof Technologies, Inc.
• Inventors: Mitola, Joseph III
• Granted Patent: US 9,519,804 B2
• Time in Patent Office: Days
• US Class Current: 726/23
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 21/56 Computer malware detection or handling, e.g. anti-virus arrangements
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06N 20/00 Machine learning
• CPC Class Codes: G06Q 20/405 Establishing or using transaction specific rules
• CPC Class Codes: H04L 47/70 Admission control; Resource allocation
• CPC Class Codes: H04L 63/123 received data contents, e.g. message integrity
• CPC Class Codes: H04L 67/02 based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

A domain-specific hardwired symbolic machine is disclosed that processes information via the flexible formation and hardwired mapping of symbols from one or more domains onto other such domains, computing and communicating with improved security because it has no CPU, no Random Access Memory (RAM), no instruction registers, no Instruction Set Architecture (ISA), no operating system (OS) and no applications programming. The machine may learn, e.g. from its users, via hardwired analysis of domain faults with associated recovery. The machine may modify itself according to interaction with its authorized authenticated users with self-modification via learning within application-specific, user-specific constraints hardwired into the original machine, eliminating configuration management and computer programming.

Claims

1. A domain-specific symbolic computing apparatus comprising:

circuitry configured to process information via symbols mapped among domains embedded into hardware of the domain-specific symbolic computing apparatus;

wherein each of the symbols is constrained and validated by the circuitry to values of the domains that are explicitly enumerated within the circuitry via a symbolic notation.

2. The domain-specific symbolic computing apparatus of claim 1, wherein the domain-specific computing apparatus has no registers;

no central processing unit (CPU);

no Random Access Memory (RAM);

no instruction registers;

no Instruction Set Architecture (ISA);

has no operating system (OS); and

has no applications programming.

3. The domain-specific symbolic computing apparatus of claim 1, further comprising the symbols, wherein the symbols include one or more fixed symbols, one or more variable symbols, or one or more null symbols, wherein the one or more fixed symbols or the one or more variable symbols refer to things, places, paths, actions, causes or events via the symbolic notation.

4. The domain-specific symbolic computing apparatus of claim 1 further comprising semantically coded symbols that are self-referentially consistent.

5. The domain-specific symbolic computing apparatus of claim 1 further comprising:

semantically coded symbols that employ conversational human language; and

hardwired circuitry configured to;

read, verify, validate, and interpret the semantically coded symbols,

employ the semantically coded symbols when communicating with portions of the hardwired circuitry, and

employ the semantically coded symbols to generate interactive dialog with users of the domain-specific symbolic computing apparatus.

6. The domain-specific symbolic computing apparatus of claim 1 further comprising:

circuitry configured to store coded and human-readable symbols, wherein the coded and human-readable symbols define a computational self-description (Self) of the domain-specific symbolic computing apparatus, wherein the (Self) is used to observe, verify and control operations of the domain-specific symbolic computing apparatus.

7. The domain-specific symbolic computing apparatus of claim 1 configured to modify its domain-specific capabilities via forms of machine learning mediated by human language.

8. The domain-specific symbolic computing apparatus of claim 1 configured to modify its domain-specific computational capabilities via forms of machine learning mediated by observation of interactions in which it has been told what to do, remembering, recalling, and modifying prior instructions to apply to a new situation.

9. The domain-specific symbolic computing apparatus of claim 1 configured to reconfigure itself according to a (Self) model of its own resources, wherein said reconfiguring integrates information accrued via previous resolution of faults into a reconfigured version of itself making such acquired information a permanent part of a reconfigured (Self).

10. The domain-specific symbolic computing apparatus of claim 1, wherein the circuitry is embodied in one or more field-programmable gate arrays (FPGA) or one or more application-specific integrated circuits (ASIC).

11. An apparatus, comprising:

one or more memory blocks configured to store symbols of textual data;

a plurality of domains that define valid values of the symbols, wherein the plurality of domains is hardwired into the apparatus;

one or more first pipe segments, wherein each of the one or more first pipe segments includes combinatorial logic, wherein each of the one or more first pipe segments is configured to process a symbol between an input memory block and an output memory block according to its combinatorial logic and verify that the textual data of the symbol is valid according to one of the plurality of domains; and

one or more second pipe segments, wherein each of the one or more second pipe segments includes combinatorial logic, wherein each of the one or more second pipe segments is configured to, via its combinatorial logic, map the textual data of a symbol from a first of the plurality of domains to a second of the plurality of domains.

12. The apparatus of claim 11, further comprising self-description circuitry that provides a description of what the apparatus can and cannot perform, wherein the plurality of domains is hardwired in the self-description circuitry.

13. The apparatus of claim 11, wherein the one or more memory blocks, the plurality of domains, the one or more first pipe segments, and the one or more second pipe segments are embodied in one or more field-programmable gate arrays (FPGA) or one or more application-specific integrated circuits (ASIC).

14. The apparatus of claim 11, wherein the one or more memory blocks, the plurality of domains, the one or more first pipe segments, and the one or more second pipe segments are arranged to perform one or more designated functions related to a software application.

15. The apparatus of claim 11, further comprising reconfiguration circuitry configured to generate an FPGA image based on a fault generated during operation of the apparatus and recompile circuitry of the apparatus.

16. A method comprising:

receiving a specification that provides a definition of an application to be implemented in an apparatus;

determining a list of domains, a list of variable objects and a list of maps based on the specification;

determining pipe circuitry for each map in the list of maps to produce a plurality of pipe circuits;

determining memory block circuitry for each variable object in the list of variable objects to produce a plurality of memory block circuits; and

implementing the plurality of pipe circuits and the plurality of memory block circuits into the apparatus such that the apparatus is capable of performing functions of the application according information processed via the plurality of memory block circuits and the plurality of pipe circuits.

17. The method of claim 16, wherein implementing the plurality of pipe circuits and the plurality of memory block circuits includes:

converting the plurality of memory block circuits and the plurality of pipe circuits into a field programmable gate array (FPGA) image, and

compiling the FPGA image into an FPGA, resulting in the DUPPL apparatus.

18. The method of claim 16 further comprising:

determining a list of constraints based on the specification; and

determining self-description circuitry based on the list of constraints, wherein the self-description defines what the DUPPL apparatus can and cannot do and includes an identification of the application;

wherein implementing the plurality of pipe circuits and the plurality of memory block circuits further includes implementing the self-description circuitry into the DUPPL apparatus.

19. The method of claim 16, wherein the plurality of pipe circuits includes a first pipe that determines whether a textual symbol is a member of a first domain from the list of domains, and a second pipe that maps a symbol from the first domain to a second domain from the list of domains.

20. The method of claim 19, wherein each pipe circuitry of the plurality of pipes comprises logic necessary to perform one or more designated functions related to the application, and wherein each memory block circuitry represents a storage location for textual symbols, wherein the textual symbols conform to a specified notation and are restricted by the plurality of pipes to being a member of at least one domain in the list of domains.