CASCADED PLL FOR REDUCING LOW-FREQUENCY DRIFT IN HOLDOVER MODE
First Claim
1. An apparatus comprising:
- a first phase-locked loop (PLL) circuit configured to generate a control signal based on a first clock signal and a first divider value;
a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value; and
a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal.
2 Assignments
0 Petitions
Accused Products
Abstract
A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.
-
Citations
27 Claims
-
1. An apparatus comprising:
-
a first phase-locked loop (PLL) circuit configured to generate a control signal based on a first clock signal and a first divider value; a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value; and a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method comprising:
-
generating a control signal by a first phase-locked loop (PLL) based on a first clock signal and a first divider value; generating the first clock signal by adjusting a controllable oscillator of a second PLL based on a phase difference between a low-jitter clock signal and the first clock signal frequency-divided according to a second divider value; and generating the second divider value based on a phase difference between a second clock signal and the first clock signal frequency-divided according to a third divider value. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
-
-
24. An apparatus comprising:
-
means for generating a control signal based on a first clock signal in response to a valid input clock signal and for generating the control signal in an absence of the valid input clock signal; means for generating the first clock signal based on a phase difference between a low-jitter reference clock signal and the first clock signal frequency-divided according to a first divider value; and means for generating the first divider value based on a second clock signal and the first clock signal frequency-divided according to a second divider value. - View Dependent Claims (25, 26, 27)
-
Specification