TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
First Claim
1. A device comprising:
- a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device;
a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; and
comparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of the plurality of reference bits.
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Accused Products
Abstract
A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.
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Citations
23 Claims
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1. A device comprising:
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a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device; a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; and comparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of the plurality of reference bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A magnetic memory device comprising:
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a plurality of data storage memory cells, the plurality of data storage memory cells configured to be accessed by commands directed to the device, each data storage memory cell of the plurality of data storage memory cells including a magnetic tunnel junction; a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device, each detection memory cell of the plurality of detection memory cells including a magnetic tunnel junction; a plurality of reference bits stored in a permanent manner on the memory device, each reference bit of the plurality of reference bits corresponding to a respective detection memory cell of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; and comparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of the plurality of reference bits. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method of operation of a memory device that includes a plurality of data storage memory cells and a plurality of detection memory cells, the method comprising:
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comparing state of each detection memory cell of the plurality of detection memory cells with a corresponding reference bit of a plurality of reference bits; determining, based on the comparing, a tamper-attempt indication corresponding to an attempt to tamper with data stored in the data storage memory cells; and in response to determining the tamper-attempt indication, generating a tamper-attempt indication signal. - View Dependent Claims (20, 21, 22, 23)
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Specification