SEMICONDUCTOR DEVICE

• US 20140226400A1
• Filed: 06/25/2013
• Published: 08/14/2014
• Est. Priority Date: 02/12/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KIMURA, Naoki
• Granted Patent: US 9,286,985 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.

Claims

1. A semiconductor device comprising:

a nonvolatile memory;

a volatile memory comprising a first area and a second area;

a first controller configured to control the nonvolatile memory and the volatile memory;

a power supply unit configured to be supplied with power from a host apparatus and to supply power to the nonvolatile memory, the volatile memory, and the first controller; and

a second controller configured to be supplied with power from the host apparatus and to control the power supply unit,

wherein when a request for transitioning from a first mode to a second mode in which power consumption is smaller than that in the first mode is received, the first controller transitions the first area of the volatile memory to a self-refresh mode and transmits a request to the volatile memory to not perform refreshing of the second area, and after that, transmits a signal to the second controller,

the second controller receives the signal from the first controller and transmits a request to the power supply unit to disconnect the power supplied to the nonvolatile memory and the first controller.

2. The device according to claim 1, wherein before the refreshing of the second area is stopped, the first controller transfers at least a part of first data in the second area to the first area, and after that, transmits the signal to the second controller.

3. The device according to claim 2, wherein the first data comprises management information of the nonvolatile memory.

4. The device according to claim 2, wherein the first data comprises at least a part of a start program of the first controller.

5. The device according to claim 2, wherein the first controller stops refreshing of the second area in a state where the second area comprises second data.

6. The device according to claim 5, wherein the second data comprises information which is readable from the nonvolatile memory.

7. The device according to claim 1, wherein the first controller does not write management information of the nonvolatile memory to the second area of the volatile memory but writes the management information to the first area in the first mode.

8. The device according to claim 1, wherein before refreshing of the second area is stopped, the first controller writes at least a part of the data of the second area in the nonvolatile memory and, after that, transmits the signal to the second controller.

9. The device according to claim 1, wherein the second controller receives a request for recovering from the second mode to the first mode and transmits a request to the power supply unit to supply power to the nonvolatile memory and the first controller.

10. A semiconductor device comprising:

a volatile memory comprising a first area and a second area; and

a controller configured to transition the first area of the volatile memory to a self-refresh mode and does not perform refreshing of the second area when a request for transitioning from a first mode to a second mode in which power consumption is smaller than that in the first mode is received.

11. The device according to claim 10, wherein before the refreshing of the second area is stopped, the controller transfers at least a part of data in the second area to the first area.

12. The device according to claim 10,

wherein the first area retains at least a part of a start program of the controller in the second mode, and

the controller is started by using the start program when a request for recovering from the second mode to the first mode is received.

13. A semiconductor device comprising:

a nonvolatile memory;

a volatile memory; and

a controller configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.