MEMORY DEVICE AND SEMICONDUCTOR DEVICE

• US 20140226401A1
• Filed: 04/21/2014
• Published: 08/14/2014
• Est. Priority Date: 08/27/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 9,449,706 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

Claims

1. (canceled)

2. A driving method for a semiconductor device, the semiconductor device comprising:

a transistor comprising an oxide semiconductor layer, a first gate electrode, and a second gate electrode; and

a memory element electrically connected to the oxide semiconductor layer,

wherein the oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode,

the driving method comprising;

applying a first potential to the first gate electrode and a second potential to the second gate electrode, respectively, during a first period; and

applying a third potential to the first gate electrode and a fourth potential to the second gate electrode, respectively, during a second period,

wherein the first potential is configured to be higher than or equal to the second potential,

wherein the first potential is configured to be higher than or equal to the third potential,

wherein the second potential is configured to be higher than or equal to the fourth potential,

wherein the third potential is configured to be higher than or equal to the fourth potential, and

wherein the second potential is configured to be lower than or equal to the third potential.

3. The driving method according to claim 2, wherein the second potential is configured to be equal to the fourth potential.

4. The driving method according to claim 2, wherein the memory element is a capacitor comprising a first electrode and a second electrode.

5. The driving method according to claim 4, further comprising:

applying a fifth potential to the second electrode during the first period; and

applying a sixth potential to the second electrode during the second period.

6. The driving method according to claim 5, wherein the fifth potential is configured to be equal to the third potential.

7. The driving method according to claim 5, wherein the fifth potential is configured to be equal to the second potential.

8. A driving method for a semiconductor device, the semiconductor device comprising:

a first transistor comprising an oxide semiconductor layer, a first gate electrode, and a second gate electrode;

a second transistor comprising a gate electrode, a source electrode and a drain electrode; and

a capacitor comprising a first electrode and a second electrode, the first electrode being electrically connected to the oxide semiconductor layer and the gate electrode,

wherein the oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode,

the driving method comprising;

applying a first potential to the first gate electrode, a second potential to the second gate electrode and a third potential to the second electrode, respectively, during a first period;

applying a fourth potential to the first gate electrode, a fifth potential to the second gate electrode and a sixth potential to the second electrode, respectively, during a second period; and

applying the fourth potential to the first gate electrode, the fifth potential to the second gate electrode and the third potential to the second electrode, respectively, during a third period,

wherein the first potential is configured to be higher than or equal to the second potential,

wherein the first potential is configured to be higher than or equal to the fourth potential,

wherein the second potential is configured to be higher than or equal to the fifth potential,

wherein the third potential is configured to be lower than the sixth potential, and

wherein the second potential is configured to be lower than or equal to the fourth potential.

9. The driving method according to claim 8, wherein the second potential is configured to be equal to the fifth potential.

10. The driving method according to claim 8, wherein the third potential is configured to be equal to the fourth potential.

11. The driving method according to claim 8, wherein the second potential is configured to be equal to the third potential.

12. The driving method according to claim 8, further comprising:

applying a seventh potential to one of the source electrode and the drain electrode during the first period;

applying the seventh potential to the one of the source electrode and the drain electrode during the second period; and

applying an eighth potential to the one of the source electrode and the drain electrode during the third period.

13. The driving method according to claim 12, wherein the eighth potential is configured to be lower than the sixth potential.

14. The driving method according to claim 12, wherein the seventh potential is configured to be lower than the eighth potential.

15. The driving method according to claim 12, wherein the seventh potential is configured to be equal to the third potential.

16. The driving method according to claim 12, wherein the seventh potential is configured to be equal to the fourth potential.

17. The driving method according to claim 12, wherein the seventh potential is configured to be equal to the second potential.