METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

• US 20140227847A1
• Filed: 03/13/2013
• Published: 08/14/2014
• Est. Priority Date: 02/14/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YOON, BO-UN, YOON, IL-YOUNG, HWANG, CHANG-SUN, KANG, BO-KYEONG, KIM, JAE-SEOK, KIM, HO-YOUNG
• Granted Patent: US 9,023,704 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin;

removing a portion of the upper pre-isolation layer by performing a first polishing process; and

planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing a remaining portion of the upper pre-isolation layer.

2. The method of claim 1, wherein a first speed at which the fin is polished by a slurry used in the second polishing process is smaller than a second speed at which the pre-isolation layer is polished by the slurry used in the second polishing process.

3. The method of claim 2, wherein the slurry includes a poly stopping slurry.

4. The method of claim 1, wherein the forming of the pre-isolation layer comprises covering a mask pattern formed on the fin with the upper pre-isolation layer.

5. The method of claim 4, wherein the removing of the portion of the upper pre-isolation layer comprises exposing the mask pattern.

6. The method of claim 5, further comprising removing the mask pattern before the performing of the second polishing process.

7. The method of claim 6, further comprising doping impurities into the fin after the removing of the mask pattern.

8. The method of claim 5, further comprising performing a densification process on a remaining portion of the upper pre-isolation layer between the removing of the portion of the upper pre-isolation layer and the performing of the second polishing process.

9. The method of claim 1, further comprising forming an isolation layer making contact with a lower portion of the fin by removing a portion of the lower pre-isolation layer.

10. The method of claim 9, wherein an upper surface of the isolation layer is substantially parallel with an upper surface of the substrate.

11. The method of claim 1, wherein the first polishing process and the second polishing process are continuously performed to remove the upper pre-isolation layer, and wherein the first polishing process and the second polishing process are performed using a poly stopping slurry.

12. A method for fabricating a semiconductor device, the method comprising:

forming a mask pattern on a substrate;

forming a fin protruding on the substrate by etching the substrate using the mask pattern;

forming a pre-isolation layer covering the fin and the mask pattern;

exposing the mask pattern by removing a portion of the pre-isolation layer by performing a first polishing process; and

planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for exposing the mask pattern and then exposing the upper surface of the fin.

13. The method of claim 12, wherein the slurry used in the second polishing process second polishing process includes a poly stopping slurry.

14. The method of claim 12, further comprising removing a portion of the isolation layer surrounding lateral surfaces of the mask pattern and removing the mask pattern, between the first polishing process and the second polishing process.

15. The method of claim 12, further comprising forming an isolation layer making contact with a lower portion of the fin by removing a portion of the pre-isolation layer after the exposing of the upper surface of the fin and wherein the substrate includes a first region and a second region, the fin is formed on the first region, and a thickness of the isolation layer formed on the first region is substantially the same as a thickness of the isolation layer formed on the second region.

16. A method for fabricating a semiconductor device, the method comprising:

forming a first mask pattern on a substrate;

forming a mask layer substantially conformally along an upper surface of the substrate having the first mask pattern;

patterning the mask layer to form a second mask pattern exposing the first mask pattern;

removing the first mask pattern to expose the substrate on both sides of the mask pattern;

forming a plurality of fins on a first region of the substrate but not on a second region of the substrate by etching the substrate using the second mask pattern;

forming a pre-isolation layer covering the fins and the second mask pattern remaining on upper surfaces of the fins;

exposing the second mask pattern by removing a portion an upper layer of the pre-isolation layer covering the fins by performing a first polishing process;

performing a densification process to oxidize the upper layer of the pre-isolation layer after exposing the second mask pattern;

removing a portion of the upper layer of the pre-isolation layer surrounding lateral surfaces of the second mask pattern;

removing the second mask pattern after removing the portion of the upper layer of the pre-isolation layer, thereby exposing the upper surfaces of the fins;

doping impurities into the fins after removing the second mask pattern;

removing the remaining portion of the upper layer of the pre-isolation layer by performing a second polishing process, thereby planarizing the pre-isolation layer such that the upper surface of the fins are coplanar with an upper surface of the pre-isolation layer; and

removing a portion of a lower layer of the pre-isolation layer to thereby form an isolation layer which contacts a lower portion of the fins and wherein the fins protrude from isolation layer.

17. A method for fabricating a fin-type field effect transistor using the semiconductor device of claim 16, comprising:

forming a dummy gate pattern extending in a first direction crossing the fins protruding from the isolation layer by an etching process using a mask pattern, wherein the dummy gate pattern includes a dummy gate insulation layer and a dummy gate electrode disposed on the dummy gate insulation layer;

forming a spacer on lateral surfaces of the dummy gate insulation layer and the dummy gate electrode;

removing a portion of the fins exposed to opposing sides of the dummy gate pattern to form a recess in the fins;

forming a source/drain region on the fins exposed to the opposing sides of the dummy gate pattern after forming the recess in the fins;

forming an interlayer insulating layer on the resultant product having the source/drain

planarizing the interlayer insulating layer until the mask pattern is removed and an upper surface of the dummy gate pattern is exposed;

removing the dummy gate insulation layer and the dummy gate electrode, thereby forming a trench exposing the isolation layer and a portion of the fins; and

sequentially forming a gate insulation layer and a gate electrode in the trench to thereby defining a gate pattern in the trench.

18. The method of claim 17, wherein the substrate is made of silicon (Si), wherein the source drain includes silicon germanium (SiGe) having a larger lattice constant than a lattice constant of silicon (Si), wherein the gate electrode includes a first metal gate layer and a second metal gate layer, wherein the first metal gate layer includes at least one selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC) and the second metal gate layer includes at least one of tungsten (W) or aluminum (Al).

19. The method of claim 17, wherein the substrate is made of silicon Si), wherein the source drain includes silicon carbide (SiC) having a smaller lattice constant than a lattice constant of silicon (Si), wherein the gate electrode includes a first metal gate layer and a second metal gate layer, wherein the first metal gate layer includes at least one selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC) and the second metal gate layer includes at least one of tungsten (W) or aluminum (Al).

20. The method of claim 17, wherein the source/drain has one of the following shapes selected from the group consisting of a hexagon, a diamond, a quadrangle, and a pentagon.